OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Diff between revs 304 and 321

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 304 Rev 321
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.49  2003/11/12 18:24:59  tadejm
 
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
 
//
// Revision 1.48  2003/10/17 07:46:16  markom
// Revision 1.48  2003/10/17 07:46:16  markom
// mbist signals updated according to newest convention
// mbist signals updated according to newest convention
//
//
// Revision 1.47  2003/10/06 15:43:45  knguyen
// Revision 1.47  2003/10/06 15:43:45  knguyen
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
Line 414... Line 417...
wire        r_TxPauseRq;    // Transmit PAUSE request
wire        r_TxPauseRq;    // Transmit PAUSE request
 
 
wire  [3:0] r_MaxRet;       //
wire  [3:0] r_MaxRet;       //
wire        r_NoBckof;      // 
wire        r_NoBckof;      // 
wire        r_ExDfrEn;      // 
wire        r_ExDfrEn;      // 
wire        TX_BD_NUM_Wr;   // Write enable that writes RX_BD_NUM to the registers.
 
wire        r_TxFlow;       // Tx flow control enable
wire        r_TxFlow;       // Tx flow control enable
wire        r_IFG;          // Minimum interframe gap for incoming packets
wire        r_IFG;          // Minimum interframe gap for incoming packets
 
 
wire        TxB_IRQ;        // Interrupt Tx Buffer
wire        TxB_IRQ;        // Interrupt Tx Buffer
wire        TxE_IRQ;        // Interrupt Tx Error
wire        TxE_IRQ;        // Interrupt Tx Error
Line 512... Line 514...
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
  .r_TxBDNum(r_TxBDNum),                  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),                .int_o(int_o),
  .r_TxBDNum(r_TxBDNum),                  .int_o(int_o),
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
  .SetPauseTimer(SetPauseTimer)
  .SetPauseTimer(SetPauseTimer)
 
 
Line 880... Line 882...
  .TxDone(TxDone),
  .TxDone(TxDone),
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
 
 
  // Register
  // Register
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),        .r_RxFlow(r_RxFlow),                      .r_PassAll(r_PassAll),
  .r_RxFlow(r_RxFlow),                      .r_PassAll(r_PassAll),
 
 
  //RX
  //RX
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.