| Line 276... |
Line 276... |
`endif
|
`endif
|
|
|
);
|
);
|
|
|
|
|
parameter Tp = 1;
|
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
|
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH;
|
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH;
|
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH;
|
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH;
|
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
|
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
|
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH;
|
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH;
|
| Line 387... |
Line 386... |
reg TxPauseRq_sync3;
|
reg TxPauseRq_sync3;
|
reg TPauseRq;
|
reg TPauseRq;
|
|
|
|
|
// Connecting Miim module
|
// Connecting Miim module
|
eth_miim #(.Tp(Tp))
|
eth_miim miim1
|
miim1
|
|
(
|
(
|
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
|
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
|
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
|
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
|
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
|
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
|
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
|
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
|
| Line 532... |
Line 530... |
`ifdef ETH_REGISTERED_OUTPUTS
|
`ifdef ETH_REGISTERED_OUTPUTS
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
temp_wb_ack_o_reg <=#Tp 1'b0;
|
temp_wb_ack_o_reg <= 1'b0;
|
temp_wb_dat_o_reg <=#Tp 32'h0;
|
temp_wb_dat_o_reg <= 32'h0;
|
temp_wb_err_o_reg <=#Tp 1'b0;
|
temp_wb_err_o_reg <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
|
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
|
temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
|
temp_wb_dat_o_reg <= temp_wb_dat_o;
|
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
|
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
// Connecting Ethernet registers
|
// Connecting Ethernet registers
|
eth_registers #(.Tp(Tp))
|
eth_registers ethreg1
|
ethreg1
|
|
(
|
(
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
|
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
| Line 605... |
Line 602... |
wire RetryLimit;
|
wire RetryLimit;
|
wire StatePreamble;
|
wire StatePreamble;
|
wire [1:0] StateData;
|
wire [1:0] StateData;
|
|
|
// Connecting MACControl
|
// Connecting MACControl
|
eth_maccontrol #(.Tp(Tp))
|
eth_maccontrol maccontrol1
|
maccontrol1
|
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
|
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
| Line 659... |
Line 655... |
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
|
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
|
|
|
|
|
|
|
// Connecting TxEthMAC
|
// Connecting TxEthMAC
|
eth_txethmac #(.Tp(Tp))
|
eth_txethmac txethmac1
|
txethmac1
|
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
|
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
| Line 694... |
Line 689... |
wire AddressMiss;
|
wire AddressMiss;
|
|
|
|
|
|
|
// Connecting RxEthMAC
|
// Connecting RxEthMAC
|
eth_rxethmac #(.Tp(Tp))
|
eth_rxethmac rxethmac1
|
rxethmac1
|
|
(
|
(
|
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
| Line 716... |
Line 710... |
// MII Carrier Sense Synchronization
|
// MII Carrier Sense Synchronization
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
CarrierSense_Tx1 <= #Tp 1'b0;
|
CarrierSense_Tx1 <= 1'b0;
|
CarrierSense_Tx2 <= #Tp 1'b0;
|
CarrierSense_Tx2 <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
CarrierSense_Tx1 <= #Tp mcrs_pad_i;
|
CarrierSense_Tx1 <= mcrs_pad_i;
|
CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
|
CarrierSense_Tx2 <= CarrierSense_Tx1;
|
end
|
end
|
end
|
end
|
|
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
|
|
|
| Line 734... |
Line 728... |
// MII Collision Synchronization
|
// MII Collision Synchronization
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
Collision_Tx1 <= #Tp 1'b0;
|
Collision_Tx1 <= 1'b0;
|
Collision_Tx2 <= #Tp 1'b0;
|
Collision_Tx2 <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Collision_Tx1 <= #Tp mcoll_pad_i;
|
Collision_Tx1 <= mcoll_pad_i;
|
if(ResetCollision)
|
if(ResetCollision)
|
Collision_Tx2 <= #Tp 1'b0;
|
Collision_Tx2 <= 1'b0;
|
else
|
else
|
if(Collision_Tx1)
|
if(Collision_Tx1)
|
Collision_Tx2 <= #Tp 1'b1;
|
Collision_Tx2 <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Synchronized Collision
|
// Synchronized Collision
|
| Line 757... |
Line 751... |
|
|
|
|
// Delayed WillTransmit
|
// Delayed WillTransmit
|
always @ (posedge mrx_clk_pad_i)
|
always @ (posedge mrx_clk_pad_i)
|
begin
|
begin
|
WillTransmit_q <= #Tp WillTransmit;
|
WillTransmit_q <= WillTransmit;
|
WillTransmit_q2 <= #Tp WillTransmit_q;
|
WillTransmit_q2 <= WillTransmit_q;
|
end
|
end
|
|
|
|
|
assign Transmitting = ~r_FullD & WillTransmit_q2;
|
assign Transmitting = ~r_FullD & WillTransmit_q2;
|
|
|
| Line 770... |
Line 764... |
|
|
// Synchronized Receive Enable
|
// Synchronized Receive Enable
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
RxEnSync <= #Tp 1'b0;
|
RxEnSync <= 1'b0;
|
else
|
else
|
if(~mrxdv_pad_i)
|
if(~mrxdv_pad_i)
|
RxEnSync <= #Tp r_RxEn;
|
RxEnSync <= r_RxEn;
|
end
|
end
|
|
|
|
|
|
|
// Synchronizing WillSendControlFrame to WB_CLK;
|
// Synchronizing WillSendControlFrame to WB_CLK;
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
WillSendControlFrame_sync1 <= 1'b0;
|
WillSendControlFrame_sync1 <= 1'b0;
|
else
|
else
|
WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
|
WillSendControlFrame_sync1 <= WillSendControlFrame;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
WillSendControlFrame_sync2 <= 1'b0;
|
WillSendControlFrame_sync2 <= 1'b0;
|
else
|
else
|
WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
|
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
WillSendControlFrame_sync3 <= 1'b0;
|
WillSendControlFrame_sync3 <= 1'b0;
|
else
|
else
|
WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
|
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
RstTxPauseRq <= 1'b0;
|
RstTxPauseRq <= 1'b0;
|
else
|
else
|
RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
|
RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
|
end
|
end
|
|
|
|
|
|
|
|
|
// TX Pause request Synchronization
|
// TX Pause request Synchronization
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
TxPauseRq_sync1 <= #Tp 1'b0;
|
TxPauseRq_sync1 <= 1'b0;
|
TxPauseRq_sync2 <= #Tp 1'b0;
|
TxPauseRq_sync2 <= 1'b0;
|
TxPauseRq_sync3 <= #Tp 1'b0;
|
TxPauseRq_sync3 <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
|
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
|
TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
|
TxPauseRq_sync2 <= TxPauseRq_sync1;
|
TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
|
TxPauseRq_sync3 <= TxPauseRq_sync2;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
TPauseRq <= #Tp 1'b0;
|
TPauseRq <= 1'b0;
|
else
|
else
|
TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
|
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
|
end
|
end
|
|
|
|
|
wire LatchedMRxErr;
|
wire LatchedMRxErr;
|
reg RxAbort_latch;
|
reg RxAbort_latch;
|
| Line 852... |
Line 846... |
|
|
// Synchronizing RxAbort to the WISHBONE clock
|
// Synchronizing RxAbort to the WISHBONE clock
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
RxAbort_latch <= #Tp 1'b0;
|
RxAbort_latch <= 1'b0;
|
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
|
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
|
RxAbort_latch <= #Tp 1'b1;
|
RxAbort_latch <= 1'b1;
|
else if(RxAbortRst)
|
else if(RxAbortRst)
|
RxAbort_latch <= #Tp 1'b0;
|
RxAbort_latch <= 1'b0;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
RxAbort_sync1 <= #Tp 1'b0;
|
RxAbort_sync1 <= 1'b0;
|
RxAbort_wb <= #Tp 1'b0;
|
RxAbort_wb <= 1'b0;
|
RxAbort_wb <= #Tp 1'b0;
|
RxAbort_wb <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxAbort_sync1 <= #Tp RxAbort_latch;
|
RxAbort_sync1 <= RxAbort_latch;
|
RxAbort_wb <= #Tp RxAbort_sync1;
|
RxAbort_wb <= RxAbort_sync1;
|
end
|
end
|
end
|
end
|
|
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
RxAbortRst_sync1 <= #Tp 1'b0;
|
RxAbortRst_sync1 <= 1'b0;
|
RxAbortRst <= #Tp 1'b0;
|
RxAbortRst <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxAbortRst_sync1 <= #Tp RxAbort_wb;
|
RxAbortRst_sync1 <= RxAbort_wb;
|
RxAbortRst <= #Tp RxAbortRst_sync1;
|
RxAbortRst <= RxAbortRst_sync1;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
// Connecting Wishbone module
|
// Connecting Wishbone module
|
eth_wishbone #(.Tp(Tp),
|
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH),
|
.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH),
|
|
.TX_FIFO_DEPTH (TX_FIFO_DEPTH),
|
.TX_FIFO_DEPTH (TX_FIFO_DEPTH),
|
.TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH),
|
.TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH),
|
.RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH),
|
.RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH),
|
.RX_FIFO_DEPTH (RX_FIFO_DEPTH),
|
.RX_FIFO_DEPTH (RX_FIFO_DEPTH),
|
.RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH))
|
.RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH))
|
| Line 957... |
Line 950... |
);
|
);
|
|
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
|
|
|
// Connecting MacStatus module
|
// Connecting MacStatus module
|
eth_macstatus #(.Tp(Tp))
|
eth_macstatus macstatus1
|
macstatus1
|
|
(
|
(
|
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
|
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
