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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_txethmac.v] - Diff between revs 72 and 79

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Rev 72 Rev 79
Line 41... Line 41...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.6  2002/02/22 12:56:35  mohor
 
// Retry is not activated when a Tx Underrun occured
 
//
// Revision 1.5  2002/02/11 09:18:22  mohor
// Revision 1.5  2002/02/11 09:18:22  mohor
// Tx status is written back to the BD.
// Tx status is written back to the BD.
//
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
// Link in the header changed.
Line 151... Line 154...
reg [3:0] RetryCnt;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg [3:0] MTxD_d;
reg StatusLatch;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished_q;
reg PacketFinished;
reg PacketFinished;
reg [3:0] RetryCntLatched;
 
 
 
 
 
wire ExcessiveDeferOccured;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartIPG;
wire StartPreamble;
wire StartPreamble;

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