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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Revision 1.2 2001/09/11 14:17:00 mohor
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module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
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module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
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TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
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TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
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TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
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TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
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ControlData, WillSendControlFrame
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ControlData, WillSendControlFrame, BlockTxDone
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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output TxCtrlEndFrm;
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output TxCtrlEndFrm;
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output SendingCtrlFrm;
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output SendingCtrlFrm;
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output CtrlMux;
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output CtrlMux;
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output [7:0] ControlData;
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output [7:0] ControlData;
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output WillSendControlFrame;
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output WillSendControlFrame;
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output BlockTxDone;
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reg SendingCtrlFrm;
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reg SendingCtrlFrm;
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reg CtrlMux;
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reg CtrlMux;
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reg WillSendControlFrame;
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reg WillSendControlFrame;
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reg [3:0] DlyCrcCnt;
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reg [3:0] DlyCrcCnt;
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reg TxCtrlStartFrm;
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reg TxCtrlStartFrm;
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reg TxCtrlStartFrm_q;
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reg TxCtrlStartFrm_q;
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reg TxCtrlEndFrm;
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reg TxCtrlEndFrm;
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reg [7:0] ControlData;
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reg [7:0] ControlData;
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reg TxUsedDataIn_q;
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reg TxUsedDataIn_q;
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reg BlockTxDone;
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wire IncrementDlyCrcCnt;
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wire IncrementDlyCrcCnt;
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wire ResetByteCnt;
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wire ResetByteCnt;
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wire IncrementByteCnt;
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wire IncrementByteCnt;
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wire ControlEnd;
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wire ControlEnd;
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TxCtrlStartFrm <= #Tp 1'b0;
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TxCtrlStartFrm <= #Tp 1'b0;
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else
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else
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if(TxUsedDataIn_q & CtrlMux)
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if(TxUsedDataIn_q & CtrlMux)
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TxCtrlStartFrm <= #Tp 1'b0;
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TxCtrlStartFrm <= #Tp 1'b0;
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else
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else
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if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | ~TxUsedDataOutDetected))
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if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
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TxCtrlStartFrm <= #Tp 1'b1;
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TxCtrlStartFrm <= #Tp 1'b1;
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end
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end
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else
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else
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TxUsedDataIn_q <= #Tp TxUsedDataIn;
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TxUsedDataIn_q <= #Tp TxUsedDataIn;
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end
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end
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// Generation of the signal that will block sending the Done signal to the eth_wishbone module
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// While sending the control frame
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always @ (posedge MTxClk or posedge TxReset)
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begin
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if(TxReset)
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BlockTxDone <= #Tp 1'b0;
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else
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if(TxCtrlStartFrm)
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BlockTxDone <= #Tp 1'b1;
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else
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if(TxDoneIn)
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BlockTxDone <= #Tp 1'b0;
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end
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always @ (posedge MTxClk)
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always @ (posedge MTxClk)
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begin
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begin
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ControlEnd_q <= #Tp ControlEnd;
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ControlEnd_q <= #Tp ControlEnd;
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TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
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TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
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end
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end
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