Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.16 2002/03/19 12:53:29 mohor
|
|
// Some defines that are used in testbench only were moved to tb_eth_defines.v
|
|
// file.
|
|
//
|
// Revision 1.15 2002/02/26 16:11:32 mohor
|
// Revision 1.15 2002/02/26 16:11:32 mohor
|
// Number of interrupts changed
|
// Number of interrupts changed
|
//
|
//
|
// Revision 1.14 2002/02/16 14:03:44 mohor
|
// Revision 1.14 2002/02/16 14:03:44 mohor
|
// Registered trimmed. Unused registers removed.
|
// Registered trimmed. Unused registers removed.
|
Line 109... |
Line 113... |
//
|
//
|
//
|
//
|
|
|
|
|
//`define EXTERNAL_DMA // Using DMA
|
//`define EXTERNAL_DMA // Using DMA
|
|
//`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
|
|
|
|
|
// Selection of the used memory
|
// Selection of the used memory
|
//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
|
//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
|
// specific elements.
|
// specific elements.
|
Line 146... |
Line 151... |
`define ETH_INT_SOURCE_DEF 32'h00000000
|
`define ETH_INT_SOURCE_DEF 32'h00000000
|
`define ETH_INT_MASK_DEF 7'h0
|
`define ETH_INT_MASK_DEF 7'h0
|
`define ETH_IPGT_DEF 7'h12
|
`define ETH_IPGT_DEF 7'h12
|
`define ETH_IPGR1_DEF 7'h0C
|
`define ETH_IPGR1_DEF 7'h0C
|
`define ETH_IPGR2_DEF 7'h12
|
`define ETH_IPGR2_DEF 7'h12
|
`define ETH_PACKETLEN_DEF 32'h003C0600
|
`define ETH_PACKETLEN_DEF 32'h00400600
|
`define ETH_COLLCONF0_DEF 6'h3f
|
`define ETH_COLLCONF0_DEF 6'h3f
|
`define ETH_COLLCONF1_DEF 4'hF
|
`define ETH_COLLCONF1_DEF 4'hF
|
`define ETH_TX_BD_NUM_DEF 8'h80
|
`define ETH_TX_BD_NUM_DEF 8'h80
|
`define ETH_CTRLMODER_DEF 3'h0
|
`define ETH_CTRLMODER_DEF 3'h0
|
`define ETH_MIIMODER_DEF 11'h064
|
`define ETH_MIIMODER_DEF 11'h064
|
Line 166... |
Line 171... |
|
|
|
|
// Outputs are registered (uncomment when needed)
|
// Outputs are registered (uncomment when needed)
|
// `define ETH_REGISTERED_OUTPUTS
|
// `define ETH_REGISTERED_OUTPUTS
|
|
|
`define TX_FIFO_CNT_WIDTH 4
|
`define TX_FIFO_CNT_WIDTH 5
|
`define TX_FIFO_DEPTH 8
|
`define TX_FIFO_DEPTH 16
|
`define TX_FIFO_DATA_WIDTH 32
|
`define TX_FIFO_DATA_WIDTH 32
|
|
|
`define RX_FIFO_CNT_WIDTH 4
|
`define RX_FIFO_CNT_WIDTH 5
|
`define RX_FIFO_DEPTH 8
|
`define RX_FIFO_DEPTH 16
|
`define RX_FIFO_DATA_WIDTH 32
|
`define RX_FIFO_DATA_WIDTH 32
|
|
|
No newline at end of file
|
No newline at end of file
|