| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.5 2002/02/08 16:21:54 mohor
|
|
// Rx status is written back to the BD.
|
|
//
|
// Revision 1.4 2002/02/06 14:10:21 mohor
|
// Revision 1.4 2002/02/06 14:10:21 mohor
|
// non-DMA host interface added. Select the right configutation in eth_defines.
|
// non-DMA host interface added. Select the right configutation in eth_defines.
|
//
|
//
|
// Revision 1.3 2002/02/05 16:44:39 mohor
|
// Revision 1.3 2002/02/05 16:44:39 mohor
|
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
|
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
|
| Line 104... |
Line 107... |
WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
|
WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
|
|
|
// Interrupts
|
// Interrupts
|
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
|
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
|
|
|
|
// Rx Status
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
ReceivedPacketTooBig, RxLength, LoadRxStatus
|
ReceivedPacketTooBig, RxLength, LoadRxStatus,
|
|
|
|
// Tx Status
|
|
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
|
|
|
);
|
);
|
|
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
| Line 137... |
Line 144... |
input m_wb_ack_i; //
|
input m_wb_ack_i; //
|
input m_wb_err_i; //
|
input m_wb_err_i; //
|
|
|
input Reset; // Reset signal
|
input Reset; // Reset signal
|
|
|
// Status signals
|
// Rx Status signals
|
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
|
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
|
input LatchedCrcError; // CRC error
|
input LatchedCrcError; // CRC error
|
input RxLateCollision; // Late collision occured while receiving frame
|
input RxLateCollision; // Late collision occured while receiving frame
|
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
|
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
|
input DribbleNibble; // Extra nibble received
|
input DribbleNibble; // Extra nibble received
|
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
|
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
|
input [15:0] RxLength; // Length of the incoming frame
|
input [15:0] RxLength; // Length of the incoming frame
|
input LoadRxStatus; // Rx status was loaded
|
input LoadRxStatus; // Rx status was loaded
|
|
|
|
// Tx Status signals
|
|
input [3:0] RetryCntLatched; // Latched Retry Counter
|
|
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
|
|
input LateCollLatched; // Late collision occured
|
|
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
|
|
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
|
|
|
// Tx
|
// Tx
|
input MTxClk; // Transmit clock (from PHY)
|
input MTxClk; // Transmit clock (from PHY)
|
input TxUsedData; // Transmit packet used data
|
input TxUsedData; // Transmit packet used data
|
input [15:0] StatusIzTxEthMACModula;
|
input [15:0] StatusIzTxEthMACModula;
|
input TxRetry; // Transmit packet retry
|
input TxRetry; // Transmit packet retry
|
| Line 193... |
Line 207... |
reg TxStartFrm;
|
reg TxStartFrm;
|
reg TxEndFrm;
|
reg TxEndFrm;
|
reg [7:0] TxData;
|
reg [7:0] TxData;
|
|
|
reg TxUnderRun;
|
reg TxUnderRun;
|
|
reg TxUnderRun_wb;
|
|
|
reg TxBDRead;
|
reg TxBDRead;
|
wire TxStatusWrite;
|
wire TxStatusWrite;
|
|
|
reg [1:0] TxValidBytesLatched;
|
reg [1:0] TxValidBytesLatched;
|
|
|
reg [15:0] TxLength;
|
reg [15:0] TxLength;
|
reg [15:0] TxStatus;
|
reg [15:0] LatchedTxLength;
|
|
reg [14:11] TxStatus;
|
|
|
reg [14:13] RxStatusOld;
|
reg [14:13] RxStatus;
|
|
|
reg TxStartFrm_wb;
|
reg TxStartFrm_wb;
|
reg TxRetry_wb;
|
reg TxRetry_wb;
|
reg TxAbort_wb;
|
reg TxAbort_wb;
|
reg TxDone_wb;
|
reg TxDone_wb;
|
| Line 570... |
Line 586... |
// Latching status from the tx buffer descriptor
|
// Latching status from the tx buffer descriptor
|
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStatus <=#Tp 15'h0;
|
TxStatus <=#Tp 4'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxBDRead)
|
if(TxEn & TxEn_q & TxBDRead)
|
TxStatus <=#Tp ram_do[15:0];
|
TxStatus <=#Tp ram_do[14:11];
|
end
|
end
|
|
|
reg ReadTxDataFromMemory;
|
reg ReadTxDataFromMemory;
|
wire WriteRxDataToMemory;
|
wire WriteRxDataToMemory;
|
|
|
| Line 609... |
Line 625... |
else
|
else
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
end
|
end
|
end
|
end
|
|
|
|
//Latching length from the buffer descriptor;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchedTxLength <=#Tp 16'h0;
|
|
else
|
|
if(TxEn & TxEn_q & TxBDRead)
|
|
LatchedTxLength <=#Tp ram_do[31:16];
|
|
end
|
|
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthLt4 = TxLength < 4;
|
assign TxLengthLt4 = TxLength < 4;
|
|
|
|
|
reg BlockingIncrementTxPointer;
|
reg BlockingIncrementTxPointer;
|
| Line 927... |
Line 953... |
// bit 12 od tx je pad
|
// bit 12 od tx je pad
|
// bit 11 od tx je crc
|
// bit 11 od tx je crc
|
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
|
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
|
// bit 9 od tx je pause request (control frame)
|
// bit 9 od tx je pause request (control frame)
|
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
|
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
|
// bit 8 od tx je defer indication
|
// bit 8 od tx je defer indication done
|
// bit 7 od tx je late collision
|
// bit 7 od tx je late collision done
|
// bit 6 od tx je retransmittion limit
|
// bit 6 od tx je retransmittion limit done
|
// bit 5 od tx je underrun
|
// bit 5 od tx je underrun done
|
// bit 4 od tx je carrier sense lost
|
// bit 4 od tx je carrier sense lost
|
// bit [3:0] od tx je retry count
|
// bit [3:0] od tx je retry count done
|
|
|
//assign TxBDReady = TxStatus[15]; // already used
|
//assign TxBDReady = TxStatus[15]; // already used
|
assign TxIRQEn = TxStatus[14];
|
assign TxIRQEn = TxStatus[14];
|
assign WrapTxStatusBit = TxStatus[13]; // ok povezan
|
assign WrapTxStatusBit = TxStatus[13]; // ok povezan
|
assign PerPacketPad = TxStatus[12]; // ok povezan
|
assign PerPacketPad = TxStatus[12]; // ok povezan
|
assign PerPacketCrcEn = TxStatus[11] & TxStatus[10]; // When last is also set // ok povezan
|
assign PerPacketCrcEn = TxStatus[11];
|
//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
|
//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
|
|
|
|
|
|
|
// RX
|
// RX
|
// bit 15 od rx je empty
|
// bit 15 od rx je empty
|
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
|
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
|
// bit 13 od rx je wrap
|
// bit 13 od rx je wrap
|
// bit 12 od rx je reserved
|
// bit 12 od rx je reserved
|
// bit 11 od rx je reserved
|
// bit 11 od rx je reserved
|
// bit 10 od rx je last (crc se doda le ce je bit 11 in hkrati bit 10)
|
// bit 10 od rx je reserved
|
// bit 9 od rx je pause request (control frame)
|
// bit 9 od rx je reserved
|
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
|
// bit 8 od rx je reserved
|
// bit 8 od rx je defer indication
|
// bit 7 od rx je reserved
|
// bit 7 od rx je late collision
|
// bit 6 od rx je underrun still missing
|
// bit 6 od rx je retransmittion limit
|
// bit 5 od rx je InvalidSymbol
|
// bit 5 od rx je underrun
|
// bit 4 od rx je DribbleNibble
|
// bit 4 od rx je carrier sense lost
|
// bit 3 od rx je ReceivedPacketTooBig
|
// bit [3:0] od rx je retry count
|
// bit 2 od rx je ShortFrame
|
|
// bit 1 od rx je LatchedCrcError
|
|
// bit 0 od rx je RxLateCollision
|
|
assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
|
|
assign WrapRxStatusBit = RxStatusOld[13];
|
assign WrapRxStatusBit = RxStatus[13];
|
|
|
|
|
// Temporary Tx and Rx buffer descriptor address
|
// Temporary Tx and Rx buffer descriptor address
|
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
|
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
|
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum) | // Using first Rx BD
|
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum) | // Using first Rx BD
|
| Line 992... |
Line 1021... |
else
|
else
|
if(RxStatusWrite)
|
if(RxStatusWrite)
|
RxBDAddress <=#Tp TempRxBDAddress;
|
RxBDAddress <=#Tp TempRxBDAddress;
|
end
|
end
|
|
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatusOld, 7'h0, RxStatusInLatched}; // tu dopolni, da se bo vpisoval status
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
|
assign TxBDDataIn = {32'h004380ef}; // tu dopolni, da se bo vpisoval status
|
|
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 7'h0, RxStatusInLatched};
|
|
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
|
|
|
|
|
// Signals used for various purposes
|
// Signals used for various purposes
|
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
| Line 1124... |
Line 1155... |
|
|
// Tx under run
|
// Tx under run
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun_wb <=#Tp 1'b0;
|
else
|
else
|
if(TxAbortPulse)
|
if(TxAbortPulse)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun_wb <=#Tp 1'b0;
|
else
|
else
|
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
|
TxUnderRun_wb <=#Tp 1'b1;
|
|
end
|
|
|
|
|
|
// Tx under run
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxUnderRun <=#Tp 1'b0;
|
|
else
|
|
if(TxUnderRun_wb)
|
TxUnderRun <=#Tp 1'b1;
|
TxUnderRun <=#Tp 1'b1;
|
|
else
|
|
if(BlockingTxStatusWrite)
|
|
TxUnderRun <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
// Tx Byte counter
|
// Tx Byte counter
|
| Line 1307... |
Line 1352... |
// Latching Rx buffer descriptor status
|
// Latching Rx buffer descriptor status
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusOld <=#Tp 2'h0;
|
RxStatus <=#Tp 2'h0;
|
else
|
else
|
if(RxEn & RxEn_q & RxBDRead)
|
if(RxEn & RxEn_q & RxBDRead)
|
RxStatusOld <=#Tp ram_do[14:13];
|
RxStatus <=#Tp ram_do[14:13];
|
end
|
end
|
|
|
|
|
|
|
|
|
| Line 1708... |
Line 1753... |
if(LoadRxStatus & ~LoadStatusBlocked)
|
if(LoadRxStatus & ~LoadStatusBlocked)
|
RxStatusInLatched <=#Tp RxStatusIn;
|
RxStatusInLatched <=#Tp RxStatusIn;
|
end
|
end
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
