| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/02/11 09:18:22 mohor
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// Tx status is written back to the BD.
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//
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// Revision 1.5 2002/02/08 16:21:54 mohor
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// Revision 1.5 2002/02/08 16:21:54 mohor
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// Rx status is written back to the BD.
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// Rx status is written back to the BD.
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//
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//
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// Revision 1.4 2002/02/06 14:10:21 mohor
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// Revision 1.4 2002/02/06 14:10:21 mohor
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// non-DMA host interface added. Select the right configutation in eth_defines.
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// non-DMA host interface added. Select the right configutation in eth_defines.
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| Line 92... |
Line 95... |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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//TX
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//TX
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, StatusIzTxEthMACModula,
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
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TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
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PerPacketPad,
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PerPacketPad,
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//RX
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//RX
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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| Line 164... |
Line 167... |
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
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input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
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// Tx
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// Tx
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input MTxClk; // Transmit clock (from PHY)
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input MTxClk; // Transmit clock (from PHY)
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input TxUsedData; // Transmit packet used data
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input TxUsedData; // Transmit packet used data
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input [15:0] StatusIzTxEthMACModula;
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input TxRetry; // Transmit packet retry
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input TxRetry; // Transmit packet retry
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input TxAbort; // Transmit packet abort
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input TxAbort; // Transmit packet abort
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input TxDone; // Transmission ended
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input TxDone; // Transmission ended
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output TxStartFrm; // Transmit packet start frame
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output TxStartFrm; // Transmit packet start frame
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output TxEndFrm; // Transmit packet end frame
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output TxEndFrm; // Transmit packet end frame
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| Line 266... |
Line 268... |
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reg WriteRxDataToFifo;
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reg WriteRxDataToFifo;
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reg [15:0] LatchedRxLength;
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reg [15:0] LatchedRxLength;
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reg ShiftEnded;
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reg ShiftEnded;
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reg RxOverrun;
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reg BDWrite; // BD Write Enable for access from WISHBONE side
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reg BDWrite; // BD Write Enable for access from WISHBONE side
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reg BDRead; // BD Read access from WISHBONE side
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reg BDRead; // BD Read access from WISHBONE side
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wire [31:0] RxBDDataIn; // Rx BD data in
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wire [31:0] RxBDDataIn; // Rx BD data in
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wire [31:0] TxBDDataIn; // Tx BD data in
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wire [31:0] TxBDDataIn; // Tx BD data in
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| Line 298... |
Line 301... |
wire SetGotData;
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wire SetGotData;
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wire GotDataEvaluate;
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wire GotDataEvaluate;
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reg temp_ack;
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reg temp_ack;
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wire [5:0] RxStatusIn;
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wire [6:0] RxStatusIn;
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reg [5:0] RxStatusInLatched;
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reg [6:0] RxStatusInLatched;
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`ifdef ETH_REGISTERED_OUTPUTS
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`ifdef ETH_REGISTERED_OUTPUTS
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reg temp_ack2;
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reg temp_ack2;
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reg [31:0] registered_ram_do;
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reg [31:0] registered_ram_do;
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`endif
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`endif
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| Line 318... |
Line 321... |
reg [7:0] ram_addr;
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reg [7:0] ram_addr;
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reg [31:0] ram_di;
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reg [31:0] ram_di;
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wire [31:0] ram_do;
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wire [31:0] ram_do;
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wire StartTxPointerRead;
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wire StartTxPointerRead;
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wire ResetTxPointerRead;
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reg TxPointerRead;
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reg TxPointerRead;
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reg TxEn_needed;
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reg TxEn_needed;
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reg RxEn_needed;
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reg RxEn_needed;
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wire StartRxPointerRead;
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wire StartRxPointerRead;
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| Line 941... |
Line 943... |
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
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if(TxRetryPulse | TxDonePulse | TxAbortPulse)
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TxValidBytesLatched <=#Tp 2'h0;
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TxValidBytesLatched <=#Tp 2'h0;
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end
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end
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// Bit 14 is used as a wrap bit. When active it indicates the last buffer descriptor in a row. After
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// using this descriptor, first BD will be used again.
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// TX
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// bit 15 od tx je ready
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// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
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// bit 13 od tx je wrap
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// bit 12 od tx je pad
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// bit 11 od tx je crc
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// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
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// bit 9 od tx je pause request (control frame)
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// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
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// bit 8 od tx je defer indication done
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// bit 7 od tx je late collision done
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// bit 6 od tx je retransmittion limit done
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// bit 5 od tx je underrun done
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// bit 4 od tx je carrier sense lost
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// bit [3:0] od tx je retry count done
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//assign TxBDReady = TxStatus[15]; // already used
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assign TxIRQEn = TxStatus[14];
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assign TxIRQEn = TxStatus[14];
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assign WrapTxStatusBit = TxStatus[13]; // ok povezan
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assign WrapTxStatusBit = TxStatus[13];
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assign PerPacketPad = TxStatus[12]; // ok povezan
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assign PerPacketPad = TxStatus[12];
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assign PerPacketCrcEn = TxStatus[11];
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assign PerPacketCrcEn = TxStatus[11];
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//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
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//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
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// RX
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// bit 15 od rx je empty
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// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
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// bit 13 od rx je wrap
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// bit 12 od rx je reserved
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// bit 11 od rx je reserved
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// bit 10 od rx je reserved
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// bit 9 od rx je reserved
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// bit 8 od rx je reserved
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// bit 7 od rx je reserved
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// bit 6 od rx je underrun still missing
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// bit 5 od rx je InvalidSymbol
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// bit 4 od rx je DribbleNibble
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// bit 3 od rx je ReceivedPacketTooBig
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// bit 2 od rx je ShortFrame
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// bit 1 od rx je LatchedCrcError
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// bit 0 od rx je RxLateCollision
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assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
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assign WrapRxStatusBit = RxStatus[13];
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assign WrapRxStatusBit = RxStatus[13];
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// Temporary Tx and Rx buffer descriptor address
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// Temporary Tx and Rx buffer descriptor address
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assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
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assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
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| Line 1023... |
Line 985... |
RxBDAddress <=#Tp TempRxBDAddress;
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RxBDAddress <=#Tp TempRxBDAddress;
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end
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end
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wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
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wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
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assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 7'h0, RxStatusInLatched};
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assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
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assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
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assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
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// Signals used for various purposes
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// Signals used for various purposes
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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| Line 1740... |
Line 1702... |
if(LoadRxStatus & ~LoadStatusBlocked)
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if(LoadRxStatus & ~LoadStatusBlocked)
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LatchedRxLength[15:0] <=#Tp RxLength[15:0];
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LatchedRxLength[15:0] <=#Tp RxLength[15:0];
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end
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end
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assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
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assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxStatusInLatched <=#Tp 'h0;
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RxStatusInLatched <=#Tp 'h0;
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| Line 1753... |
Line 1714... |
if(LoadRxStatus & ~LoadStatusBlocked)
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if(LoadRxStatus & ~LoadStatusBlocked)
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RxStatusInLatched <=#Tp RxStatusIn;
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RxStatusInLatched <=#Tp RxStatusIn;
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end
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end
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// Rx overrun
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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RxOverrun <=#Tp 1'b0;
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else
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if(RxStatusWrite)
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RxOverrun <=#Tp 1'b0;
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else
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if(RxBufferFull & WriteRxDataToFifo_wb)
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RxOverrun <=#Tp 1'b1;
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end
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// TX
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// bit 15 od tx je ready
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// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
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// bit 13 od tx je wrap
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// bit 12 od tx je pad
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// bit 11 od tx je crc
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// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
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// bit 9 od tx je pause request (control frame)
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// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
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// bit 8 od tx je defer indication done
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// bit 7 od tx je late collision done
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// bit 6 od tx je retransmittion limit done
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// bit 5 od tx je underrun done
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// bit 4 od tx je carrier sense lost
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// bit [3:0] od tx je retry count done
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// RX
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// bit 15 od rx je empty
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// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
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// bit 13 od rx je wrap
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// bit 12 od rx je reserved
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// bit 11 od rx je reserved
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// bit 10 od rx je reserved
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// bit 9 od rx je reserved
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// bit 8 od rx je reserved
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// bit 7 od rx je reserved
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// bit 6 od rx je RxOverrun
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// bit 5 od rx je InvalidSymbol
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// bit 4 od rx je DribbleNibble
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// bit 3 od rx je ReceivedPacketTooBig
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// bit 2 od rx je ShortFrame
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// bit 1 od rx je LatchedCrcError
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// bit 0 od rx je RxLateCollision
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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