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https://opencores.org/ocsvn/ethmac/ethmac/trunk
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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//
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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// demands).
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//
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//
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//
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//
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//
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// Selection of the used memory
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//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
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// specific elements.
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`define ETH_FPGA // Core is going to be implemented in FPGA and contains FPGA specific elements
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
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// Should be cleared for the ASIC implementation
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`define ETH_MODER_ADR 6'h0 // 0x0
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`define ETH_MODER_ADR 6'h0 // 0x0
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`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
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`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
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`define ETH_INT_MASK_ADR 6'h2 // 0x8
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`define ETH_INT_MASK_ADR 6'h2 // 0x8
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