URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [tags/] [rel_11/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 118 and 119
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 118 |
Rev 119 |
Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.29 2002/07/20 00:41:32 mohor
|
|
// ShiftEnded synchronization changed.
|
|
//
|
// Revision 1.28 2002/07/18 16:11:46 mohor
|
// Revision 1.28 2002/07/18 16:11:46 mohor
|
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
|
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
|
//
|
//
|
// Revision 1.27 2002/07/11 02:53:20 mohor
|
// Revision 1.27 2002/07/11 02:53:20 mohor
|
// RxPointer bug fixed.
|
// RxPointer bug fixed.
|
Line 424... |
Line 427... |
end
|
end
|
|
|
assign WB_DAT_O = ram_do;
|
assign WB_DAT_O = ram_do;
|
|
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
generic_spram #(8, 32) ram (
|
eth_spram_256x32 bd_ram (
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
|
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
|
);
|
);
|
|
|
assign ram_ce = 1'b1;
|
assign ram_ce = 1'b1;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.