Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.39 2002/10/11 15:35:20 mohor
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// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
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// TxDone and TxRetry are generated after the current WISHBONE access is
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// finished.
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//
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// Revision 1.38 2002/10/10 16:29:30 mohor
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// Revision 1.38 2002/10/10 16:29:30 mohor
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// BIST added.
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// BIST added.
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//
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//
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// Revision 1.37 2002/09/11 14:18:46 mohor
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// Revision 1.37 2002/09/11 14:18:46 mohor
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// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
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// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
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Line 356... |
Line 361... |
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reg TxDone_wb_q;
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reg TxDone_wb_q;
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reg TxAbort_wb_q;
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reg TxAbort_wb_q;
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reg TxRetry_wb_q;
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reg TxRetry_wb_q;
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reg TxRetryPacket;
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reg TxRetryPacket;
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reg TxDonePulse_q;
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reg TxRetryPacket_NotCleared;
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reg TxDonePacket;
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reg TxDonePacket_NotCleared;
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reg TxAbortPacket;
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reg TxAbortPacket;
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reg TxAbortPacket_NotCleared;
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reg RxBDReady;
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reg RxBDReady;
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reg RxReady;
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reg RxReady;
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reg TxBDReady;
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reg TxBDReady;
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reg RxBDRead;
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reg RxBDRead;
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Line 620... |
Line 628... |
TxBDReady <=#Tp 1'b0;
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TxBDReady <=#Tp 1'b0;
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end
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end
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// Reading the Tx buffer descriptor
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// Reading the Tx buffer descriptor
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assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
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assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxBDRead <=#Tp 1'b1;
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TxBDRead <=#Tp 1'b1;
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Line 653... |
Line 661... |
TxPointerRead <=#Tp 1'b0;
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TxPointerRead <=#Tp 1'b0;
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end
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end
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// Writing status back to the Tx buffer descriptor
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// Writing status back to the Tx buffer descriptor
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assign TxStatusWrite = (TxDone_wb | TxAbort_wb) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
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assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
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// Status writing must occur only once. Meanwhile it is blocked.
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// Status writing must occur only once. Meanwhile it is blocked.
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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Line 877... |
Line 885... |
else
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else
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if(SetReadTxDataFromMemory)
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if(SetReadTxDataFromMemory)
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ReadTxDataFromMemory <=#Tp 1'b1;
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ReadTxDataFromMemory <=#Tp 1'b1;
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end
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end
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wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
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reg BlockingLastReadOn_Abort_Retry;
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wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
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wire [31:0] TxData_wb;
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wire [31:0] TxData_wb;
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wire ReadTxDataFromFifo_wb;
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wire ReadTxDataFromFifo_wb;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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else
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else
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if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
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if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
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BlockReadTxDataFromMemory <=#Tp 1'b1;
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BlockReadTxDataFromMemory <=#Tp 1'b1;
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else
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else
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if(ReadTxDataFromFifo_wb | TxDonePulse_q | TxAbortPacket | TxRetryPacket)
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if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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end
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
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else
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if(TxAbortPacket | TxRetryPacket)
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BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
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else
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if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
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BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
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end
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
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wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
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wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
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wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
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Line 1009... |
Line 1034... |
begin
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begin
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MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
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MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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cyc_cleared<=#Tp 1'b0;
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IncrTxPointer<=#Tp 1'b0;
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IncrTxPointer<=#Tp 1'b0;
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end
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end
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default: // Don't touch
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default: // Don't touch
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begin
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begin
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MasterWbTX <=#Tp MasterWbTX;
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MasterWbTX <=#Tp MasterWbTX;
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Line 1126... |
Line 1152... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxEndFrm_wb <=#Tp 1'b0;
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TxEndFrm_wb <=#Tp 1'b0;
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else
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else
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if(TxLengthLt4 & TxBufferAlmostEmpty & TxUsedData)
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if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
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TxEndFrm_wb <=#Tp 1'b1;
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TxEndFrm_wb <=#Tp 1'b1;
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else
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else
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if(TxRetryPulse | TxDonePulse | TxAbortPulse)
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if(TxRetryPulse | TxDonePulse | TxAbortPulse)
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TxEndFrm_wb <=#Tp 1'b0;
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TxEndFrm_wb <=#Tp 1'b0;
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end
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end
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Line 1252... |
Line 1278... |
if(Reset)
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if(Reset)
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begin
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begin
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TxDone_wb_q <=#Tp 1'b0;
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TxDone_wb_q <=#Tp 1'b0;
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TxAbort_wb_q <=#Tp 1'b0;
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TxAbort_wb_q <=#Tp 1'b0;
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TxRetry_wb_q <=#Tp 1'b0;
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TxRetry_wb_q <=#Tp 1'b0;
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TxDonePulse_q <=#Tp 1'b0;
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end
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end
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else
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else
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begin
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begin
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TxDone_wb_q <=#Tp TxDone_wb;
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TxDone_wb_q <=#Tp TxDone_wb;
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TxAbort_wb_q <=#Tp TxAbort_wb;
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TxAbort_wb_q <=#Tp TxAbort_wb;
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TxRetry_wb_q <=#Tp TxRetry_wb;
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TxRetry_wb_q <=#Tp TxRetry_wb;
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TxDonePulse_q <=#Tp TxDonePulse;
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end
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end
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end
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end
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reg TxAbortPacketBlocked;
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reg TxAbortPacketBlocked;
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Line 1280... |
Line 1304... |
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxAbortPacket_NotCleared <=#Tp 1'b0;
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else
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if(TxAbort_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
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TxAbortPacket_NotCleared <=#Tp 1'b1;
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else
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TxAbortPacket_NotCleared <=#Tp 1'b0;
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxAbortPacketBlocked <=#Tp 1'b0;
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TxAbortPacketBlocked <=#Tp 1'b0;
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else
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else
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if(TxAbortPacket)
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if(TxAbortPacket)
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TxAbortPacketBlocked <=#Tp 1'b1;
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TxAbortPacketBlocked <=#Tp 1'b1;
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else
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else
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Line 1306... |
Line 1342... |
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxRetryPacket_NotCleared <=#Tp 1'b0;
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else
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if(TxRetry_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
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TxRetryPacket_NotCleared <=#Tp 1'b1;
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else
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TxRetryPacket_NotCleared <=#Tp 1'b0;
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxRetryPacketBlocked <=#Tp 1'b0;
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TxRetryPacketBlocked <=#Tp 1'b0;
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else
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else
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if(TxRetryPacket)
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if(TxRetryPacket)
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TxRetryPacketBlocked <=#Tp 1'b1;
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TxRetryPacketBlocked <=#Tp 1'b1;
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else
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else
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if(!TxRetry_wb & TxRetry_wb_q)
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if(!TxRetry_wb & TxRetry_wb_q)
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TxRetryPacketBlocked <=#Tp 1'b0;
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TxRetryPacketBlocked <=#Tp 1'b0;
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end
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end
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reg TxDonePacketBlocked;
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxDonePacket <=#Tp 1'b0;
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else
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if(TxDone_wb & (!TxDonePacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
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TxDonePacket <=#Tp 1'b1;
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else
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TxDonePacket <=#Tp 1'b0;
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxDonePacket_NotCleared <=#Tp 1'b0;
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else
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if(TxDone_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
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TxDonePacket_NotCleared <=#Tp 1'b1;
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else
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TxDonePacket_NotCleared <=#Tp 1'b0;
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxDonePacketBlocked <=#Tp 1'b0;
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else
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if(TxDonePacket)
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TxDonePacketBlocked <=#Tp 1'b1;
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else
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if(!TxDone_wb & TxDone_wb_q)
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TxDonePacketBlocked <=#Tp 1'b0;
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end
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// Sinchronizing and evaluating tx data
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// Sinchronizing and evaluating tx data
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//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
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//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
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assign SetGotData = (TxStartFrm_wb);
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assign SetGotData = (TxStartFrm_wb);
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// Evaluating data. If abort or retry occured meanwhile than data is ignored.
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// Evaluating data. If abort or retry occured meanwhile than data is ignored.
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Line 2007... |
Line 2093... |
);
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);
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assign WriteRxDataToMemory = ~RxBufferEmpty;
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assign WriteRxDataToMemory = ~RxBufferEmpty;
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// Generation of the end-of-frame signal
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// Generation of the end-of-frame signal
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ShiftEnded_rck <=#Tp 1'b0;
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ShiftEnded_rck <=#Tp 1'b0;
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