Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.38 2002/10/10 16:29:30 mohor
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// BIST added.
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//
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// Revision 1.37 2002/09/11 14:18:46 mohor
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// Revision 1.37 2002/09/11 14:18:46 mohor
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// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
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// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
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//
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//
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// Revision 1.36 2002/09/10 13:48:46 mohor
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// Revision 1.36 2002/09/10 13:48:46 mohor
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// Reception is possible after RxPointer is read and not after BD is read. For
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// Reception is possible after RxPointer is read and not after BD is read. For
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Line 192... |
Line 195... |
// WISHBONE master
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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`ifdef ETH_WISHBONE_B3
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m_wb_cti_o, m_wb_bte_o,
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`endif
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//TX
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//TX
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
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TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
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PerPacketPad,
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PerPacketPad,
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Line 248... |
Line 255... |
output m_wb_stb_o; //
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output m_wb_stb_o; //
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input [31:0] m_wb_dat_i; //
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input [31:0] m_wb_dat_i; //
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input m_wb_ack_i; //
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input m_wb_ack_i; //
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input m_wb_err_i; //
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input m_wb_err_i; //
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`ifdef ETH_WISHBONE_B3
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output [2:0] m_wb_cti_o; // Cycle Type Identifier
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output [1:0] m_wb_bte_o; // Burst Type Extension
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reg [2:0] m_wb_cti_o; // Cycle Type Identifier
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`endif
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input Reset; // Reset signal
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input Reset; // Reset signal
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// Rx Status signals
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// Rx Status signals
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input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
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input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
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input LatchedCrcError; // CRC error
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input LatchedCrcError; // CRC error
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Line 342... |
Line 355... |
reg TxDone_wb;
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reg TxDone_wb;
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reg TxDone_wb_q;
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reg TxDone_wb_q;
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reg TxAbort_wb_q;
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reg TxAbort_wb_q;
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reg TxRetry_wb_q;
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reg TxRetry_wb_q;
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reg TxDone_wb_q2;
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reg TxRetryPacket;
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reg TxAbort_wb_q2;
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reg TxDonePulse_q;
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reg TxRetry_wb_q2;
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reg TxAbortPacket;
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reg RxBDReady;
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reg RxBDReady;
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reg RxReady;
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reg RxReady;
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reg TxBDReady;
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reg TxBDReady;
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reg RxBDRead;
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reg RxBDRead;
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Line 399... |
Line 412... |
reg TxEndFrm_wb;
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reg TxEndFrm_wb;
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wire TxRetryPulse;
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wire TxRetryPulse;
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wire TxDonePulse;
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wire TxDonePulse;
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wire TxAbortPulse;
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wire TxAbortPulse;
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wire TxRetryPulse_q;
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wire TxDonePulse_q;
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wire TxAbortPulse_q;
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wire StartRxBDRead;
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wire StartRxBDRead;
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wire StartTxBDRead;
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wire StartTxBDRead;
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Line 445... |
Line 455... |
reg RxEn_needed;
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reg RxEn_needed;
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wire StartRxPointerRead;
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wire StartRxPointerRead;
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reg RxPointerRead;
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reg RxPointerRead;
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`ifdef ETH_WISHBONE_B3
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assign m_wb_bte_o = 2'b00; // Linear burst
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`endif
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always @ (posedge WB_CLK_I)
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always @ (posedge WB_CLK_I)
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begin
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begin
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WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
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WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
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end
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end
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Line 457... |
Line 471... |
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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eth_spram_256x32 bd_ram (
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eth_spram_256x32 bd_ram (
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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, .trst(trst), .SO(SO), .SI(SI), .shift_DR(.shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
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, .trst(trst), .SO(SO), .SI(SI), .shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
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`endif
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`endif
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);
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);
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assign ram_ce = 1'b1;
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assign ram_ce = 1'b1;
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assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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Line 845... |
Line 859... |
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wire TxBufferAlmostFull;
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wire TxBufferAlmostFull;
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wire TxBufferFull;
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wire TxBufferFull;
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wire TxBufferEmpty;
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wire TxBufferEmpty;
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wire TxBufferAlmostEmpty;
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wire TxBufferAlmostEmpty;
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wire ResetReadTxDataFromMemory;
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wire SetReadTxDataFromMemory;
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wire SetReadTxDataFromMemory;
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reg BlockReadTxDataFromMemory;
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reg BlockReadTxDataFromMemory;
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|
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assign ResetReadTxDataFromMemory = (TxLengthEq0) | TxAbortPulse_q | TxRetryPulse_q;
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assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
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assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ReadTxDataFromMemory <=#Tp 1'b0;
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ReadTxDataFromMemory <=#Tp 1'b0;
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else
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else
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if(ResetReadTxDataFromMemory)
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if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
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ReadTxDataFromMemory <=#Tp 1'b0;
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ReadTxDataFromMemory <=#Tp 1'b0;
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else
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else
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if(SetReadTxDataFromMemory)
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if(SetReadTxDataFromMemory)
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ReadTxDataFromMemory <=#Tp 1'b1;
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ReadTxDataFromMemory <=#Tp 1'b1;
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end
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end
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Line 874... |
Line 886... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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else
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else
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if(ReadTxDataFromFifo_wb | ResetReadTxDataFromMemory)
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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else
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if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
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if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
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BlockReadTxDataFromMemory <=#Tp 1'b1;
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BlockReadTxDataFromMemory <=#Tp 1'b1;
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else
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if(ReadTxDataFromFifo_wb | TxDonePulse_q | TxAbortPacket | TxRetryPacket)
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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end
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end
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
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wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
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// Enabling master wishbone access to the memory for two devices TX and RX.
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// Enabling master wishbone access to the memory for two devices TX and RX.
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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Line 1013... |
Line 1027... |
end
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end
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wire TxFifoClear;
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wire TxFifoClear;
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assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
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assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
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wire [4:0] txfifo_cnt;
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eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
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eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
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tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
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tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
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.clk(WB_CLK_I), .reset(Reset),
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.clk(WB_CLK_I), .reset(Reset),
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.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb),
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.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
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.clear(TxFifoClear), .full(TxBufferFull),
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.clear(TxFifoClear), .full(TxBufferFull),
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.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
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.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
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.empty(TxBufferEmpty), .cnt(txfifo_cnt)
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.empty(TxBufferEmpty), .cnt(txfifo_cnt)
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);
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);
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Line 1211... |
Line 1224... |
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// Signals used for various purposes
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// Signals used for various purposes
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
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assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
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assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
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assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
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assign TxRetryPulse_q = TxRetry_wb_q & ~TxRetry_wb_q2;
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assign TxDonePulse_q = TxDone_wb_q & ~TxDone_wb_q2;
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assign TxAbortPulse_q = TxAbort_wb_q & ~TxAbort_wb_q2;
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// Generating delayed signals
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// Generating delayed signals
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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Line 1242... |
Line 1252... |
if(Reset)
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if(Reset)
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begin
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begin
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TxDone_wb_q <=#Tp 1'b0;
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TxDone_wb_q <=#Tp 1'b0;
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TxAbort_wb_q <=#Tp 1'b0;
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TxAbort_wb_q <=#Tp 1'b0;
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TxRetry_wb_q <=#Tp 1'b0;
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TxRetry_wb_q <=#Tp 1'b0;
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TxDone_wb_q2 <=#Tp 1'b0;
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TxDonePulse_q <=#Tp 1'b0;
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TxAbort_wb_q2 <=#Tp 1'b0;
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TxRetry_wb_q2 <=#Tp 1'b0;
|
|
end
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end
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else
|
else
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begin
|
begin
|
TxDone_wb_q <=#Tp TxDone_wb;
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TxDone_wb_q <=#Tp TxDone_wb;
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TxAbort_wb_q <=#Tp TxAbort_wb;
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TxAbort_wb_q <=#Tp TxAbort_wb;
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TxRetry_wb_q <=#Tp TxRetry_wb;
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TxRetry_wb_q <=#Tp TxRetry_wb;
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TxDone_wb_q2 <=#Tp TxDone_wb_q;
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TxDonePulse_q <=#Tp TxDonePulse;
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TxAbort_wb_q2 <=#Tp TxAbort_wb_q;
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TxRetry_wb_q2 <=#Tp TxRetry_wb_q;
|
|
end
|
end
|
end
|
end
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|
|
|
|
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reg TxAbortPacketBlocked;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
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TxAbortPacket <=#Tp 1'b0;
|
|
else
|
|
if(TxAbort_wb & (!TxAbortPacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
|
|
TxAbortPacket <=#Tp 1'b1;
|
|
else
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TxAbortPacket <=#Tp 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxAbortPacketBlocked <=#Tp 1'b0;
|
|
else
|
|
if(TxAbortPacket)
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|
TxAbortPacketBlocked <=#Tp 1'b1;
|
|
else
|
|
if(!TxAbort_wb & TxAbort_wb_q)
|
|
TxAbortPacketBlocked <=#Tp 1'b0;
|
|
end
|
|
|
|
|
|
reg TxRetryPacketBlocked;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxRetryPacket <=#Tp 1'b0;
|
|
else
|
|
if(TxRetry_wb & (!TxRetryPacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
|
|
TxRetryPacket <=#Tp 1'b1;
|
|
else
|
|
TxRetryPacket <=#Tp 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxRetryPacketBlocked <=#Tp 1'b0;
|
|
else
|
|
if(TxRetryPacket)
|
|
TxRetryPacketBlocked <=#Tp 1'b1;
|
|
else
|
|
if(!TxRetry_wb & TxRetry_wb_q)
|
|
TxRetryPacketBlocked <=#Tp 1'b0;
|
|
end
|
|
|
|
|
// Sinchronizing and evaluating tx data
|
// Sinchronizing and evaluating tx data
|
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
|
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
|
assign SetGotData = (TxStartFrm_wb); // igor namesto zgornje
|
assign SetGotData = (TxStartFrm_wb);
|
|
|
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
|
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
|
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
|
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
|
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
|
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
|
|
|
Line 1936... |
Line 1994... |
end
|
end
|
|
|
|
|
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
|
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
|
|
|
wire [4:0] rxfifo_cnt;
|
|
|
|
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
|
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk(WB_CLK_I), .reset(Reset),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
|
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
|
);
|
);
|
|
|
assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;
|
assign WriteRxDataToMemory = ~RxBufferEmpty;
|
|
|
|
|
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
Line 2040... |
Line 2097... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSync1 <=#Tp 1'b0;
|
RxAbortSync1 <=#Tp 1'b0;
|
else
|
else
|
// RxAbortSync1 <=#Tp RxAbort;
|
|
RxAbortSync1 <=#Tp RxAbortLatched;
|
RxAbortSync1 <=#Tp RxAbortLatched;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|