Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/01/23 10:28:16 mohor
|
|
// Link in the header changed.
|
|
//
|
// Revision 1.3 2001/10/19 08:43:51 mohor
|
// Revision 1.3 2001/10/19 08:43:51 mohor
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// simulation of the few cores in a one joined project.
|
// simulation of the few cores in a one joined project.
|
//
|
//
|
// Revision 1.2 2001/09/11 14:17:00 mohor
|
// Revision 1.2 2001/09/11 14:17:00 mohor
|
Line 75... |
Line 78... |
|
|
|
|
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
|
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
|
RxData, RxValid, RxStartFrm, RxEndFrm, CrcHash, CrcHashGood, Broadcast,
|
RxData, RxValid, RxStartFrm, RxEndFrm, CrcHash, CrcHashGood, Broadcast,
|
Multicast, ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
|
Multicast, ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
|
CrcError, StateIdle, StatePreamble, StateSFD, StateData
|
CrcError, StateIdle, StatePreamble, StateSFD, StateData,
|
|
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort
|
);
|
);
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
|
|
|
Line 91... |
Line 95... |
input HugEn;
|
input HugEn;
|
input DlyCrcEn;
|
input DlyCrcEn;
|
input [15:0] MaxFL;
|
input [15:0] MaxFL;
|
input r_IFG;
|
input r_IFG;
|
input Reset;
|
input Reset;
|
|
input [47:0] MAC; // Station Address
|
|
input r_Bro; // broadcast disable
|
|
input r_Pro; // promiscuous enable
|
|
input [31:0] r_HASH0; // lower 4 bytes Hash Table
|
|
input [31:0] r_HASH1; // upper 4 bytes Hash Table
|
output [7:0] RxData;
|
output [7:0] RxData;
|
output RxValid;
|
output RxValid;
|
output RxStartFrm;
|
output RxStartFrm;
|
output RxEndFrm;
|
output RxEndFrm;
|
output [8:0] CrcHash;
|
output [8:0] CrcHash;
|
Line 109... |
Line 117... |
output CrcError;
|
output CrcError;
|
output StateIdle;
|
output StateIdle;
|
output StatePreamble;
|
output StatePreamble;
|
output StateSFD;
|
output StateSFD;
|
output [1:0] StateData;
|
output [1:0] StateData;
|
|
output RxAbort;
|
|
|
reg [7:0] RxData;
|
reg [7:0] RxData;
|
reg RxValid;
|
reg RxValid;
|
reg RxStartFrm;
|
reg RxStartFrm;
|
reg RxEndFrm;
|
reg RxEndFrm;
|
Line 130... |
Line 139... |
|
|
wire MRxDEqD;
|
wire MRxDEqD;
|
wire MRxDEq5;
|
wire MRxDEq5;
|
wire StateDrop;
|
wire StateDrop;
|
wire ByteCntEq1;
|
wire ByteCntEq1;
|
|
wire ByteCntEq2;
|
|
wire ByteCntEq3;
|
|
wire ByteCntEq4;
|
|
wire ByteCntEq5;
|
wire ByteCntEq6;
|
wire ByteCntEq6;
|
|
wire ByteCntEq7;
|
wire ByteCntSmall7;
|
wire ByteCntSmall7;
|
wire [31:0] Crc;
|
wire [31:0] Crc;
|
wire Enable_Crc;
|
wire Enable_Crc;
|
wire Initialize_Crc;
|
wire Initialize_Crc;
|
wire [3:0] Data_Crc;
|
wire [3:0] Data_Crc;
|
wire GenerateRxValid;
|
wire GenerateRxValid;
|
wire GenerateRxStartFrm;
|
wire GenerateRxStartFrm;
|
wire GenerateRxEndFrm;
|
wire GenerateRxEndFrm;
|
wire DribbleRxEndFrm;
|
wire DribbleRxEndFrm;
|
wire [3:0] DlyCrcCnt;
|
wire [3:0] DlyCrcCnt;
|
|
wire RxAbort;
|
|
|
|
|
assign MRxDEqD = MRxD == 4'hd;
|
assign MRxDEqD = MRxD == 4'hd;
|
assign MRxDEq5 = MRxD == 4'h5;
|
assign MRxDEq5 = MRxD == 4'h5;
|
|
|
Line 163... |
Line 177... |
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
|
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
|
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
|
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
|
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
|
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
|
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
|
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
|
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
|
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
|
.ByteCntEq1(ByteCntEq1), .ByteCntEq6(ByteCntEq6), .ByteCntGreat2(ByteCntGreat2),
|
.ByteCntEq1(ByteCntEq1),
|
|
.ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
|
|
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
|
|
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),.ByteCntGreat2(ByteCntGreat2),
|
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
|
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
|
.ByteCnt(ByteCnt)
|
.ByteCnt(ByteCnt)
|
);
|
);
|
|
|
|
// Rx Address Check
|
|
|
|
eth_rxaddrcheck rxaddrcheck1(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
|
|
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
|
|
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
|
|
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
|
|
.HASH0(r_HASH0), .HASH1(r_HASH1),
|
|
.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood),.StateData(StateData),
|
|
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
|
|
.RxEndFrm(RxEndFrm)
|
|
);
|
|
|
|
|
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
|
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
|
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
|
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
|
|
|
Line 243... |
Line 271... |
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
|
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
|
Broadcast <= #Tp 1'b0;
|
Broadcast <= #Tp 1'b0;
|
else
|
else
|
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
|
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
|
Broadcast <= #Tp 1'b1;
|
Broadcast <= #Tp 1'b1;
|
|
else
|
|
if(RxAbort | RxEndFrm)
|
|
Broadcast <= #Tp 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
Line 256... |
Line 287... |
else
|
else
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
Multicast <= #Tp 1'b0;
|
Multicast <= #Tp 1'b0;
|
else
|
else
|
if(StateData[0] & ByteCntEq1)
|
if(StateData[0] & ByteCntEq1 & LatchedByte == 8'h01)
|
Multicast <= #Tp LatchedByte[0];
|
Multicast <= #Tp 1'b1;
|
|
else if(RxAbort | RxEndFrm)
|
|
Multicast <= #Tp 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
|
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
|