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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 166 and 167
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Rev 166 |
Rev 167 |
Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.36 2002/09/10 13:48:46 mohor
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// Reception is possible after RxPointer is read and not after BD is read. For
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// that reason RxBDReady is changed to RxReady.
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// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
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// comes, interrupt is generated.
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//
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// Revision 1.35 2002/09/10 10:35:23 mohor
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// Revision 1.35 2002/09/10 10:35:23 mohor
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// Ethernet debug registers removed.
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// Ethernet debug registers removed.
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//
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//
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// Revision 1.34 2002/09/08 16:31:49 mohor
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// Revision 1.34 2002/09/08 16:31:49 mohor
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// Async reset for WB_ACK_O removed (when core was in reset, it was
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// Async reset for WB_ACK_O removed (when core was in reset, it was
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Line 2147... |
Line 2153... |
begin
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begin
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if(Reset)
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if(Reset)
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RxB_IRQ <=#Tp 1'b0;
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RxB_IRQ <=#Tp 1'b0;
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else
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else
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if(RxStatusWrite & RxIRQEn)
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if(RxStatusWrite & RxIRQEn)
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RxB_IRQ <=#Tp ReceivedPacketGood;
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RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
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else
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else
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RxB_IRQ <=#Tp 1'b0;
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RxB_IRQ <=#Tp 1'b0;
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end
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end
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