Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.48 2003/01/20 12:05:26 mohor
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// When in full duplex, transmit was sometimes blocked. Fixed.
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//
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// Revision 1.47 2002/11/22 13:26:21 mohor
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// Revision 1.47 2002/11/22 13:26:21 mohor
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// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
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// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
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// anywhere. Removed.
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// anywhere. Removed.
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//
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//
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// Revision 1.46 2002/11/22 01:57:06 mohor
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// Revision 1.46 2002/11/22 01:57:06 mohor
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Line 242... |
Line 245... |
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//RX
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//RX
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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// Register
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// Register
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow,
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
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// Interrupts
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// Interrupts
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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// Rx Status
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// Rx Status
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Line 316... |
Line 319... |
input [15:0] RxLength; // Length of the incoming frame
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input [15:0] RxLength; // Length of the incoming frame
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input LoadRxStatus; // Rx status was loaded
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input LoadRxStatus; // Rx status was loaded
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input ReceivedPacketGood;// Received packet's length and CRC are good
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input ReceivedPacketGood;// Received packet's length and CRC are good
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input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
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input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
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input r_RxFlow;
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input r_RxFlow;
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input r_PassAll;
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input ReceivedPauseFrm;
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input ReceivedPauseFrm;
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// Tx Status signals
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// Tx Status signals
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input [3:0] RetryCntLatched; // Latched Retry Counter
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input [3:0] RetryCntLatched; // Latched Retry Counter
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input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
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input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
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Line 2418... |
Line 2422... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxB_IRQ <=#Tp 1'b0;
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RxB_IRQ <=#Tp 1'b0;
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else
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else
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if(RxStatusWrite & RxIRQEn)
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if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
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RxB_IRQ <=#Tp ReceivedPacketGood & (~RxError) & (~r_RxFlow); // When r_RxFlow is set, RXC irq is set.
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RxB_IRQ <=#Tp (~RxError);
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else
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else
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RxB_IRQ <=#Tp 1'b0;
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RxB_IRQ <=#Tp 1'b0;
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end
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end
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Line 2431... |
Line 2435... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxE_IRQ <=#Tp 1'b0;
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RxE_IRQ <=#Tp 1'b0;
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else
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else
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if(RxStatusWrite & RxIRQEn)
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if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
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RxE_IRQ <=#Tp RxError;
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RxE_IRQ <=#Tp RxError;
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else
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else
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RxE_IRQ <=#Tp 1'b0;
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RxE_IRQ <=#Tp 1'b0;
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end
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end
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Line 2477... |
Line 2481... |
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assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
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assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
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// TX
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// bit 15 ready
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// bit 14 interrupt
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// bit 13 wrap
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// bit 12 pad
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// bit 11 crc
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// bit 10 last
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// bit 9 pause request (control frame)
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// bit 8 TxUnderRun
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// bit 7-4 RetryCntLatched
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// bit 3 retransmittion limit
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// bit 2 LateCollLatched
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// bit 1 DeferLatched
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// bit 0 CarrierSenseLost
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// RX
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// bit 15 od rx je empty
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// bit 14 od rx je interrupt
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// bit 13 od rx je wrap
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// bit 12 od rx je reserved
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// bit 11 od rx je reserved
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// bit 10 od rx je reserved
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// bit 9 od rx je reserved
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// bit 8 od rx je reserved
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// bit 7 od rx je Miss
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// bit 6 od rx je RxOverrun
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// bit 5 od rx je InvalidSymbol
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// bit 4 od rx je DribbleNibble
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// bit 3 od rx je ReceivedPacketTooBig
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// bit 2 od rx je ShortFrame
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// bit 1 od rx je LatchedCrcError
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// bit 0 od rx je RxLateCollision
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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