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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 41 and 42

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Rev 41 Rev 42
Line 39... Line 39... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.4  2002/02/06 14:10:21  mohor
 
 
 
// non-DMA host interface added. Select the right configutation in eth_defines.
 
 
 
//
 
// Revision 1.3  2002/02/05 16:44:39  mohor
 
// Revision 1.3  2002/02/05 16:44:39  mohor
 
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
 
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
 
// MHz. Statuses, overrun, control frame transmission and reception still  need
 
// MHz. Statuses, overrun, control frame transmission and reception still  need
 
// to be fixed.
 
// to be fixed.
 
//
 
//
Line 94... Line 97... 
 
 
 
 
    //RX
 
    //RX
 
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
 
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
 
 
 
 
 
    // Register
 
    // Register
 
    r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr,
 
    r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, r_RecSmall,
 
 
 
 
 
    WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
 
    WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
 
 
 
 
 
    // Interrupts
 
    // Interrupts
 
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ
 
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
 
 
 
 
 
 
 
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
 
 
 
    ReceivedPacketTooBig, RxLength, LoadRxStatus
 
 
 
 
 
                );
 
                );
 
 
 
 
 
 
 
 
 
parameter Tp = 1;
 
parameter Tp = 1;
Line 131... Line 137... 
input           m_wb_ack_i;     // 
input           m_wb_ack_i;     // 
input           m_wb_err_i;     // 
input           m_wb_err_i;     // 
 
 
 
 
input           Reset;       // Reset signal
 
input           Reset;       // Reset signal
 
 
 
 
 
 
 
// Status signals
 
 
 
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
 
// DMA
 
input           LatchedCrcError;  // CRC error
 
// input   [1:0]   WB_ACK_I;       // DMA acknowledge input
 
input           RxLateCollision;  // Late collision occured while receiving frame
 
// output  [1:0]   WB_REQ_O;       // DMA request output
 
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
 
// output  [1:0]   WB_ND_O;        // DMA force new descriptor output
 
input           DribbleNibble;    // Extra nibble received
 
// output          WB_RD_O;        // DMA restart descriptor output
 
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
 
 
 
input    [15:0] RxLength;         // Length of the incoming frame
 
 
 
input           LoadRxStatus;     // Rx status was loaded
 
 
 
 
 
// Tx
 
// Tx
 
input           MTxClk;         // Transmit clock (from PHY)
 
input           MTxClk;         // Transmit clock (from PHY)
 
input           TxUsedData;     // Transmit packet used data
 
input           TxUsedData;     // Transmit packet used data
 
input  [15:0]   StatusIzTxEthMACModula;
 
input  [15:0]   StatusIzTxEthMACModula;
Line 171... Line 179... 
input           r_TxEn;         // Transmit enable
 
input           r_TxEn;         // Transmit enable
 
input           r_RxEn;         // Receive enable
 
input           r_RxEn;         // Receive enable
 
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
 
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
 
input           r_DmaEn;        // DMA enable
 
input           r_DmaEn;        // DMA enable
 
input           TX_BD_NUM_Wr;   // RxBDNumber written
 
input           TX_BD_NUM_Wr;   // RxBDNumber written
 
 
 
input           r_RecSmall;     // Receive small frames igor !!! tega uporabi
 
 
 
 
 
// Interrupts
 
// Interrupts
 
output TxB_IRQ;
 
output TxB_IRQ;
 
output TxE_IRQ;
 
output TxE_IRQ;
 
output RxB_IRQ;
 
output RxB_IRQ;
Line 193... Line 202... 
reg     [1:0]   TxValidBytesLatched;
 
reg     [1:0]   TxValidBytesLatched;
 
 
 
 
 
reg    [15:0]   TxLength;
 
reg    [15:0]   TxLength;
 
reg    [15:0]   TxStatus;
 
reg    [15:0]   TxStatus;
 
 
 
 
 
reg    [15:0]   RxStatus;
 
reg   [14:13]   RxStatusOld;
 
 
 
 
 
reg             TxStartFrm_wb;
 
reg             TxStartFrm_wb;
 
reg             TxRetry_wb;
 
reg             TxRetry_wb;
 
reg             TxAbort_wb;
 
reg             TxAbort_wb;
 
reg             TxDone_wb;
 
reg             TxDone_wb;
Line 238... Line 247... 
reg     [1:0]   RxByteCnt;
 
reg     [1:0]   RxByteCnt;
 
reg             LastByteIn;
 
reg             LastByteIn;
 
reg             ShiftWillEnd;
 
reg             ShiftWillEnd;
 
 
 
 
 
reg             WriteRxDataToFifo;
 
reg             WriteRxDataToFifo;
 
 
 
reg    [15:0]   LatchedRxLength;
 
 
 
 
 
reg             ShiftEnded;
 
reg             ShiftEnded;
 
 
 
 
 
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
 
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
 
reg             BDRead;                     // BD Read access from WISHBONE side
 
reg             BDRead;                     // BD Read access from WISHBONE side
Line 267... Line 277... 
wire    [1:0]   TxValidBytes;
 
wire    [1:0]   TxValidBytes;
 
 
 
 
 
wire    [7:0]   TempTxBDAddress;
 
wire    [7:0]   TempTxBDAddress;
 
wire    [7:0]   TempRxBDAddress;
 
wire    [7:0]   TempRxBDAddress;
 
 
 
 
 
reg    [15:0]   RxLength;
 
 
 
wire   [15:0]   NewRxStatus;
 
 
 
 
 
 
 
wire            SetGotData;
 
wire            SetGotData;
 
wire            GotDataEvaluate;
 
wire            GotDataEvaluate;
 
 
 
 
 
reg             temp_ack;
 
reg             temp_ack;
 
 
 
 
 
 
 
wire    [5:0]   RxStatusIn;
 
 
 
reg     [5:0]   RxStatusInLatched;
 
 
 
 
 
`ifdef ETH_REGISTERED_OUTPUTS
 
`ifdef ETH_REGISTERED_OUTPUTS
 
reg             temp_ack2;
 
reg             temp_ack2;
 
reg [31:0]      registered_ram_do;
 
reg [31:0]      registered_ram_do;
 
`endif
 
`endif
 
 
 
 
Line 354... Line 364... 
  if(TxPointerRead & TxEn & TxEn_q)
 
  if(TxPointerRead & TxEn & TxEn_q)
 
    TxEn_needed <=#Tp 1'b0;
 
    TxEn_needed <=#Tp 1'b0;
 
end
 
end
 
 
 
 
 
 
 
 
 
reg [3:0] debug;
 
 
 
 
 
 
 
// Enabling access to the RAM for three devices.
 
// Enabling access to the RAM for three devices.
 
always @ (posedge WB_CLK_I or posedge Reset)
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    begin
 
    begin
 
      WbEn <=#Tp 1'b1;
 
      WbEn <=#Tp 1'b1;
 
      RxEn <=#Tp 1'b0;
 
      RxEn <=#Tp 1'b0;
 
      TxEn <=#Tp 1'b0;
 
      TxEn <=#Tp 1'b0;
 
      ram_addr <=#Tp 8'h0;
 
      ram_addr <=#Tp 8'h0;
 
      ram_di <=#Tp 32'h0;
 
      ram_di <=#Tp 32'h0;
 
 debug <=#Tp 4'h0;
 
 
 
    end
 
    end
 
  else
 
  else
 
    begin
 
    begin
 
      // Switching between three stages depends on enable signals
 
      // Switching between three stages depends on enable signals
 
      casex ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
 
      casex ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
Line 379... Line 386... 
            WbEn <=#Tp 1'b0;
 
            WbEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
 
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
 
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
 
            ram_di <=#Tp RxBDDataIn;
 
            ram_di <=#Tp RxBDDataIn;
 
 debug <=#Tp 4'h1;
 
 
 
          end
 
          end
 
        5'b100_01 :
 
        5'b100_01 :
 
          begin
 
          begin
 
            WbEn <=#Tp 1'b0;
 
            WbEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
 
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
 
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
 
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
 
            ram_di <=#Tp TxBDDataIn;
 
            ram_di <=#Tp TxBDDataIn;
 
 debug <=#Tp 4'h2;
 
 
 
          end
 
          end
 
        5'b010_x0 :
 
        5'b010_x0 :
 
          begin
 
          begin
 
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
 
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_di <=#Tp WB_DAT_I;
 
            ram_di <=#Tp WB_DAT_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
 debug <=#Tp 4'h3;
 
 
 
          end
 
          end
 
        5'b010_x1 :
 
        5'b010_x1 :
 
          begin
 
          begin
 
            WbEn <=#Tp 1'b0;
 
            WbEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
 
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
 
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
 
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
 
            ram_di <=#Tp TxBDDataIn;
 
            ram_di <=#Tp TxBDDataIn;
 
 debug <=#Tp 4'h4;
 
 
 
          end
 
          end
 
        5'b001_xx :
 
        5'b001_xx :
 
          begin
 
          begin
 
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
 
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_di <=#Tp WB_DAT_I;
 
            ram_di <=#Tp WB_DAT_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
 debug <=#Tp 4'h5;
 
 
 
          end
 
          end
 
        5'b100_00 :
 
        5'b100_00 :
 
          begin
 
          begin
 
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
 
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
 
 debug <=#Tp 4'h6;
 
 
 
          end
 
          end
 
        5'b000_00 :
 
        5'b000_00 :
 
          begin
 
          begin
 
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
 
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_di <=#Tp WB_DAT_I;
 
            ram_di <=#Tp WB_DAT_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
 debug <=#Tp 4'h7;
 
 
 
          end
 
          end
 
        default :
 
        default :
 
          begin
 
          begin
 
            WbEn <=#Tp 1'b1;  // We go to wb access stage
 
            WbEn <=#Tp 1'b1;  // We go to wb access stage
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_di <=#Tp WB_DAT_I;
 
            ram_di <=#Tp WB_DAT_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
 debug <=#Tp 4'h8;
 
 
 
          end
 
          end
 
      endcase
 
      endcase
 
    end
 
    end
 
end
 
end
 
 
 
 
Line 960... Line 959... 
// bit 6  od rx je retransmittion limit
 
// bit 6  od rx je retransmittion limit
 
// bit 5  od rx je underrun
 
// bit 5  od rx je underrun
 
// bit 4  od rx je carrier sense lost
 
// bit 4  od rx je carrier sense lost
 
// bit [3:0] od rx je retry count
 
// bit [3:0] od rx je retry count
 
 
 
 
 
assign WrapRxStatusBit = RxStatus[13];
 
assign WrapRxStatusBit = RxStatusOld[13];
 
 
 
 
 
 
 
 
 
// Temporary Tx and Rx buffer descriptor address 
// Temporary Tx and Rx buffer descriptor address 
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
 
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
 
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum)       | // Using first Rx BD
 
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum)       | // Using first Rx BD
Line 993... Line 992... 
  else
 
  else
 
  if(RxStatusWrite)
 
  if(RxStatusWrite)
 
    RxBDAddress <=#Tp TempRxBDAddress;
 
    RxBDAddress <=#Tp TempRxBDAddress;
 
end
 
end
 
 
 
 
 
assign NewRxStatus[15:0] = 16'hdead;
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatusOld, 7'h0, RxStatusInLatched};  // tu dopolni, da se bo vpisoval status
 
 
 
 
 
 
 
 
 
assign RxBDDataIn = {RxLength, NewRxStatus};  // tu dopolni, da se bo vpisoval status
 
 
 
assign TxBDDataIn = {32'h004380ef};   // tu dopolni, da se bo vpisoval status
 
assign TxBDDataIn = {32'h004380ef};   // tu dopolni, da se bo vpisoval status
 
 
 
 
 
 
 
 
 
// Signals used for various purposes
 
// Signals used for various purposes
 
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
 
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
Line 1311... Line 1307... 
// Latching Rx buffer descriptor status
 
// Latching Rx buffer descriptor status
 
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
 
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
 
always @ (posedge WB_CLK_I or posedge Reset)
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    RxStatus <=#Tp 16'h0;
 
    RxStatusOld <=#Tp 2'h0;
 
  else
 
  else
 
  if(RxEn & RxEn_q & RxBDRead)
 
  if(RxEn & RxEn_q & RxBDRead)
 
    RxStatus <=#Tp ram_do[15:0];
 
    RxStatusOld <=#Tp ram_do[14:13];
 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Line 1382... Line 1378... 
 
 
 
 
 
 
 
 
// Reception status is written back to the buffer descriptor after the end of frame is detected.
 
// Reception status is written back to the buffer descriptor after the end of frame is detected.
 
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
 
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
 
 
 
 
 
 
 
reg RxStatusWriteLatched;
 
 
 
reg RxStatusWrite_rck;
 
 
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
 
 
begin
 
 
 
  if(Reset)
 
 
 
    RxStatusWriteLatched <=#Tp 1'b0;
 
 
 
  else
 
 
 
  if(RxStatusWrite)
 
 
 
    RxStatusWriteLatched <=#Tp 1'b1;
 
 
 
  else
 
 
 
  if(RxStatusWrite_rck)
 
 
 
    RxStatusWriteLatched <=#Tp 1'b0;
 
 
 
end
 
 
 
 
 
 
 
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
 
 
 
begin
 
 
 
  if(Reset)
 
 
 
    RxStatusWrite_rck <=#Tp 1'b0;
 
 
 
  else
 
 
 
    RxStatusWrite_rck <=#Tp RxStatusWriteLatched;
 
 
 
end
 
 
 
 
 
 
 
 
 
reg RxEnableWindow;
 
reg RxEnableWindow;
 
 
 
 
 
// Indicating that last byte is being reveived
 
// Indicating that last byte is being reveived
 
always @ (posedge MRxClk or posedge Reset)
 
always @ (posedge MRxClk or posedge Reset)
 
begin
 
begin
Line 1482... Line 1503... 
      2 : RxDataLatched2 <=#Tp { 16'h0, RxDataLatched1[15:0]};
 
      2 : RxDataLatched2 <=#Tp { 16'h0, RxDataLatched1[15:0]};
 
      3 : RxDataLatched2 <=#Tp {  8'h0, RxDataLatched1[23:0]};
 
      3 : RxDataLatched2 <=#Tp {  8'h0, RxDataLatched1[23:0]};
 
    endcase
 
    endcase
 
end
 
end
 
 
 
 
 
// Assembling data that will be written to the rx_fifo
 
 
 
always @ (posedge MRxClk or posedge Reset)
 
 
 
begin
 
 
 
  if(Reset)
 
 
 
    RxLength <=#Tp 16'h0;
 
 
 
  else
 
 
 
  if(RxStartFrm)
 
 
 
    RxLength <=#Tp 16'h1;
 
 
 
  else
 
 
 
  if(RxValid & (RxStartFrm | RxEnableWindow))
 
 
 
    RxLength <=#Tp RxLength + 1'b1;
 
 
 
end
 
 
 
 
 
 
 
 
 
 
 
reg WriteRxDataToFifoSync1;
 
reg WriteRxDataToFifoSync1;
 
reg WriteRxDataToFifoSync2;
 
reg WriteRxDataToFifoSync2;
 
 
 
 
 
 
 
 
Line 1662... Line 1670... 
assign RxB_IRQ = 1'b0;
 
assign RxB_IRQ = 1'b0;
 
assign RxF_IRQ = 1'b0;
 
assign RxF_IRQ = 1'b0;
 
assign Busy_IRQ = 1'b0;
 
assign Busy_IRQ = 1'b0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
reg LoadStatusBlocked;
 
 
 
always @ (posedge MRxClk or posedge Reset)
 
 
 
begin
 
 
 
  if(Reset)
 
 
 
    LoadStatusBlocked <=#Tp 1'b0;
 
 
 
  else
 
 
 
  if(LoadRxStatus)
 
 
 
    LoadStatusBlocked <=#Tp 1'b1;
 
 
 
  else
 
 
 
  if(RxStatusWrite_rck)
 
 
 
    LoadStatusBlocked <=#Tp 1'b0;
 
 
 
end
 
 
 
 
 
 
 
// LatchedRxLength[15:0]
 
 
 
always @ (posedge MRxClk or posedge Reset)
 
 
 
begin
 
 
 
  if(Reset)
 
 
 
    LatchedRxLength[15:0] <=#Tp 16'h0;
 
 
 
  else
 
 
 
  if(LoadRxStatus & ~LoadStatusBlocked)
 
 
 
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
 
 
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
 
 
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
 
 
 
begin
 
 
 
  if(Reset)
 
 
 
    RxStatusInLatched <=#Tp 'h0;
 
 
 
  else
 
 
 
  if(LoadRxStatus & ~LoadStatusBlocked)
 
 
 
    RxStatusInLatched <=#Tp RxStatusIn;
 
 
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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