| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.8 2002/02/14 20:54:33 billditt
|
|
// Addition of new module eth_addrcheck.v
|
|
//
|
|
// Revision 1.7 2002/02/12 17:03:47 mohor
|
|
// RxOverRun added to statuses.
|
|
//
|
|
// Revision 1.6 2002/02/11 09:18:22 mohor
|
|
// Tx status is written back to the BD.
|
|
//
|
// Revision 1.5 2002/02/08 16:21:54 mohor
|
// Revision 1.5 2002/02/08 16:21:54 mohor
|
// Rx status is written back to the BD.
|
// Rx status is written back to the BD.
|
//
|
//
|
// Revision 1.4 2002/02/06 14:10:21 mohor
|
// Revision 1.4 2002/02/06 14:10:21 mohor
|
// non-DMA host interface added. Select the right configutation in eth_defines.
|
// non-DMA host interface added. Select the right configutation in eth_defines.
|
| Line 92... |
Line 101... |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
|
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
|
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
|
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
|
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
|
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
|
|
|
//TX
|
//TX
|
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, StatusIzTxEthMACModula,
|
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
|
TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
|
TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
|
PerPacketPad,
|
PerPacketPad,
|
|
|
//RX
|
//RX
|
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
|
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
|
| Line 107... |
Line 116... |
WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
|
WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
|
|
|
// Interrupts
|
// Interrupts
|
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
|
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
|
|
|
|
// Rx Status
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
ReceivedPacketTooBig, RxLength, LoadRxStatus
|
ReceivedPacketTooBig, RxLength, LoadRxStatus,
|
|
|
|
// Tx Status
|
|
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
|
|
|
);
|
);
|
|
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
| Line 140... |
Line 153... |
input m_wb_ack_i; //
|
input m_wb_ack_i; //
|
input m_wb_err_i; //
|
input m_wb_err_i; //
|
|
|
input Reset; // Reset signal
|
input Reset; // Reset signal
|
|
|
// Status signals
|
// Rx Status signals
|
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
|
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
|
input LatchedCrcError; // CRC error
|
input LatchedCrcError; // CRC error
|
input RxLateCollision; // Late collision occured while receiving frame
|
input RxLateCollision; // Late collision occured while receiving frame
|
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
|
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
|
input DribbleNibble; // Extra nibble received
|
input DribbleNibble; // Extra nibble received
|
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
|
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
|
input [15:0] RxLength; // Length of the incoming frame
|
input [15:0] RxLength; // Length of the incoming frame
|
input LoadRxStatus; // Rx status was loaded
|
input LoadRxStatus; // Rx status was loaded
|
|
|
|
// Tx Status signals
|
|
input [3:0] RetryCntLatched; // Latched Retry Counter
|
|
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
|
|
input LateCollLatched; // Late collision occured
|
|
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
|
|
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
|
|
|
// Tx
|
// Tx
|
input MTxClk; // Transmit clock (from PHY)
|
input MTxClk; // Transmit clock (from PHY)
|
input TxUsedData; // Transmit packet used data
|
input TxUsedData; // Transmit packet used data
|
input [15:0] StatusIzTxEthMACModula;
|
|
input TxRetry; // Transmit packet retry
|
input TxRetry; // Transmit packet retry
|
input TxAbort; // Transmit packet abort
|
input TxAbort; // Transmit packet abort
|
input TxDone; // Transmission ended
|
input TxDone; // Transmission ended
|
output TxStartFrm; // Transmit packet start frame
|
output TxStartFrm; // Transmit packet start frame
|
output TxEndFrm; // Transmit packet end frame
|
output TxEndFrm; // Transmit packet end frame
|
| Line 196... |
Line 215... |
reg TxStartFrm;
|
reg TxStartFrm;
|
reg TxEndFrm;
|
reg TxEndFrm;
|
reg [7:0] TxData;
|
reg [7:0] TxData;
|
|
|
reg TxUnderRun;
|
reg TxUnderRun;
|
|
reg TxUnderRun_wb;
|
|
|
reg TxBDRead;
|
reg TxBDRead;
|
wire TxStatusWrite;
|
wire TxStatusWrite;
|
|
|
reg [1:0] TxValidBytesLatched;
|
reg [1:0] TxValidBytesLatched;
|
|
|
reg [15:0] TxLength;
|
reg [15:0] TxLength;
|
reg [15:0] TxStatus;
|
reg [15:0] LatchedTxLength;
|
|
reg [14:11] TxStatus;
|
|
|
reg [14:13] RxStatusOld;
|
reg [14:13] RxStatus;
|
|
|
reg TxStartFrm_wb;
|
reg TxStartFrm_wb;
|
reg TxRetry_wb;
|
reg TxRetry_wb;
|
reg TxAbort_wb;
|
reg TxAbort_wb;
|
reg TxDone_wb;
|
reg TxDone_wb;
|
| Line 253... |
Line 274... |
|
|
reg WriteRxDataToFifo;
|
reg WriteRxDataToFifo;
|
reg [15:0] LatchedRxLength;
|
reg [15:0] LatchedRxLength;
|
|
|
reg ShiftEnded;
|
reg ShiftEnded;
|
|
reg RxOverrun;
|
|
|
reg BDWrite; // BD Write Enable for access from WISHBONE side
|
reg BDWrite; // BD Write Enable for access from WISHBONE side
|
reg BDRead; // BD Read access from WISHBONE side
|
reg BDRead; // BD Read access from WISHBONE side
|
wire [31:0] RxBDDataIn; // Rx BD data in
|
wire [31:0] RxBDDataIn; // Rx BD data in
|
wire [31:0] TxBDDataIn; // Tx BD data in
|
wire [31:0] TxBDDataIn; // Tx BD data in
|
| Line 285... |
Line 307... |
wire SetGotData;
|
wire SetGotData;
|
wire GotDataEvaluate;
|
wire GotDataEvaluate;
|
|
|
reg temp_ack;
|
reg temp_ack;
|
|
|
wire [5:0] RxStatusIn;
|
wire [6:0] RxStatusIn;
|
reg [5:0] RxStatusInLatched;
|
reg [6:0] RxStatusInLatched;
|
|
|
`ifdef ETH_REGISTERED_OUTPUTS
|
`ifdef ETH_REGISTERED_OUTPUTS
|
reg temp_ack2;
|
reg temp_ack2;
|
reg [31:0] registered_ram_do;
|
reg [31:0] registered_ram_do;
|
`endif
|
`endif
|
| Line 305... |
Line 327... |
reg [7:0] ram_addr;
|
reg [7:0] ram_addr;
|
reg [31:0] ram_di;
|
reg [31:0] ram_di;
|
wire [31:0] ram_do;
|
wire [31:0] ram_do;
|
|
|
wire StartTxPointerRead;
|
wire StartTxPointerRead;
|
wire ResetTxPointerRead;
|
|
reg TxPointerRead;
|
reg TxPointerRead;
|
reg TxEn_needed;
|
reg TxEn_needed;
|
reg RxEn_needed;
|
reg RxEn_needed;
|
|
|
wire StartRxPointerRead;
|
wire StartRxPointerRead;
|
| Line 573... |
Line 594... |
// Latching status from the tx buffer descriptor
|
// Latching status from the tx buffer descriptor
|
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStatus <=#Tp 15'h0;
|
TxStatus <=#Tp 4'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxBDRead)
|
if(TxEn & TxEn_q & TxBDRead)
|
TxStatus <=#Tp ram_do[15:0];
|
TxStatus <=#Tp ram_do[14:11];
|
end
|
end
|
|
|
reg ReadTxDataFromMemory;
|
reg ReadTxDataFromMemory;
|
wire WriteRxDataToMemory;
|
wire WriteRxDataToMemory;
|
|
|
| Line 612... |
Line 633... |
else
|
else
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
end
|
end
|
end
|
end
|
|
|
|
//Latching length from the buffer descriptor;
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchedTxLength <=#Tp 16'h0;
|
|
else
|
|
if(TxEn & TxEn_q & TxBDRead)
|
|
LatchedTxLength <=#Tp ram_do[31:16];
|
|
end
|
|
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthLt4 = TxLength < 4;
|
assign TxLengthLt4 = TxLength < 4;
|
|
|
|
|
reg BlockingIncrementTxPointer;
|
reg BlockingIncrementTxPointer;
|
| Line 918... |
Line 949... |
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
TxValidBytesLatched <=#Tp 2'h0;
|
TxValidBytesLatched <=#Tp 2'h0;
|
end
|
end
|
|
|
|
|
// Bit 14 is used as a wrap bit. When active it indicates the last buffer descriptor in a row. After
|
|
// using this descriptor, first BD will be used again.
|
|
|
|
// TX
|
|
// bit 15 od tx je ready
|
|
// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
|
|
// bit 13 od tx je wrap
|
|
// bit 12 od tx je pad
|
|
// bit 11 od tx je crc
|
|
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
|
|
// bit 9 od tx je pause request (control frame)
|
|
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
|
|
// bit 8 od tx je defer indication
|
|
// bit 7 od tx je late collision
|
|
// bit 6 od tx je retransmittion limit
|
|
// bit 5 od tx je underrun
|
|
// bit 4 od tx je carrier sense lost
|
|
// bit [3:0] od tx je retry count
|
|
|
|
//assign TxBDReady = TxStatus[15]; // already used
|
|
assign TxIRQEn = TxStatus[14];
|
assign TxIRQEn = TxStatus[14];
|
assign WrapTxStatusBit = TxStatus[13]; // ok povezan
|
assign WrapTxStatusBit = TxStatus[13];
|
assign PerPacketPad = TxStatus[12]; // ok povezan
|
assign PerPacketPad = TxStatus[12];
|
assign PerPacketCrcEn = TxStatus[11] & TxStatus[10]; // When last is also set // ok povezan
|
assign PerPacketCrcEn = TxStatus[11];
|
//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
|
//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
|
|
|
|
|
|
assign WrapRxStatusBit = RxStatus[13];
|
// RX
|
|
// bit 15 od rx je empty
|
|
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
|
|
// bit 13 od rx je wrap
|
|
// bit 12 od rx je reserved
|
|
// bit 11 od rx je reserved
|
|
// bit 10 od rx je last (crc se doda le ce je bit 11 in hkrati bit 10)
|
|
// bit 9 od rx je pause request (control frame)
|
|
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
|
|
// bit 8 od rx je defer indication
|
|
// bit 7 od rx je late collision
|
|
// bit 6 od rx je retransmittion limit
|
|
// bit 5 od rx je underrun
|
|
// bit 4 od rx je carrier sense lost
|
|
// bit [3:0] od rx je retry count
|
|
|
|
assign WrapRxStatusBit = RxStatusOld[13];
|
|
|
|
|
|
// Temporary Tx and Rx buffer descriptor address
|
// Temporary Tx and Rx buffer descriptor address
|
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
|
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
|
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum) | // Using first Rx BD
|
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum) | // Using first Rx BD
|
| Line 995... |
Line 989... |
else
|
else
|
if(RxStatusWrite)
|
if(RxStatusWrite)
|
RxBDAddress <=#Tp TempRxBDAddress;
|
RxBDAddress <=#Tp TempRxBDAddress;
|
end
|
end
|
|
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatusOld, 7'h0, RxStatusInLatched}; // tu dopolni, da se bo vpisoval status
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
|
assign TxBDDataIn = {32'h004380ef}; // tu dopolni, da se bo vpisoval status
|
|
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
|
|
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
|
|
|
|
|
// Signals used for various purposes
|
// Signals used for various purposes
|
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
| Line 1127... |
Line 1123... |
|
|
// Tx under run
|
// Tx under run
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun_wb <=#Tp 1'b0;
|
else
|
else
|
if(TxAbortPulse)
|
if(TxAbortPulse)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun_wb <=#Tp 1'b0;
|
else
|
else
|
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
|
TxUnderRun_wb <=#Tp 1'b1;
|
|
end
|
|
|
|
|
|
// Tx under run
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxUnderRun <=#Tp 1'b0;
|
|
else
|
|
if(TxUnderRun_wb)
|
TxUnderRun <=#Tp 1'b1;
|
TxUnderRun <=#Tp 1'b1;
|
|
else
|
|
if(BlockingTxStatusWrite)
|
|
TxUnderRun <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
// Tx Byte counter
|
// Tx Byte counter
|
| Line 1310... |
Line 1320... |
// Latching Rx buffer descriptor status
|
// Latching Rx buffer descriptor status
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusOld <=#Tp 2'h0;
|
RxStatus <=#Tp 2'h0;
|
else
|
else
|
if(RxEn & RxEn_q & RxBDRead)
|
if(RxEn & RxEn_q & RxBDRead)
|
RxStatusOld <=#Tp ram_do[14:13];
|
RxStatus <=#Tp ram_do[14:13];
|
end
|
end
|
|
|
|
|
|
|
|
|
| Line 1698... |
Line 1708... |
if(LoadRxStatus & ~LoadStatusBlocked)
|
if(LoadRxStatus & ~LoadStatusBlocked)
|
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
|
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
|
end
|
end
|
|
|
|
|
|
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusInLatched <=#Tp 'h0;
|
RxStatusInLatched <=#Tp 'h0;
|
| Line 1711... |
Line 1720... |
if(LoadRxStatus & ~LoadStatusBlocked)
|
if(LoadRxStatus & ~LoadStatusBlocked)
|
RxStatusInLatched <=#Tp RxStatusIn;
|
RxStatusInLatched <=#Tp RxStatusIn;
|
end
|
end
|
|
|
|
|
|
// Rx overrun
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxOverrun <=#Tp 1'b0;
|
|
else
|
|
if(RxStatusWrite)
|
|
RxOverrun <=#Tp 1'b0;
|
|
else
|
|
if(RxBufferFull & WriteRxDataToFifo_wb)
|
|
RxOverrun <=#Tp 1'b1;
|
|
end
|
|
|
|
|
|
// TX
|
|
// bit 15 od tx je ready
|
|
// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
|
|
// bit 13 od tx je wrap
|
|
// bit 12 od tx je pad
|
|
// bit 11 od tx je crc
|
|
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
|
|
// bit 9 od tx je pause request (control frame)
|
|
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
|
|
// bit 8 od tx je defer indication done
|
|
// bit 7 od tx je late collision done
|
|
// bit 6 od tx je retransmittion limit done
|
|
// bit 5 od tx je underrun done
|
|
// bit 4 od tx je carrier sense lost
|
|
// bit [3:0] od tx je retry count done
|
|
|
|
|
|
// RX
|
|
// bit 15 od rx je empty
|
|
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
|
|
// bit 13 od rx je wrap
|
|
// bit 12 od rx je reserved
|
|
// bit 11 od rx je reserved
|
|
// bit 10 od rx je reserved
|
|
// bit 9 od rx je reserved
|
|
// bit 8 od rx je reserved
|
|
// bit 7 od rx je reserved
|
|
// bit 6 od rx je RxOverrun
|
|
// bit 5 od rx je InvalidSymbol
|
|
// bit 4 od rx je DribbleNibble
|
|
// bit 3 od rx je ReceivedPacketTooBig
|
|
// bit 2 od rx je ShortFrame
|
|
// bit 1 od rx je LatchedCrcError
|
|
// bit 0 od rx je RxLateCollision
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
