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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 61 and 64

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Rev 61	Rev 64
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.10 2002/02/15 12:17:39 mohor`
	`// RxStartFrm cleared when abort or retry comes.`
	`//`
`// Revision 1.9 2002/02/15 11:59:10 mohor`	`// Revision 1.9 2002/02/15 11:59:10 mohor`
`// Changes that were lost when updating from 1.5 to 1.8 fixed.`	`// Changes that were lost when updating from 1.5 to 1.8 fixed.`
`//`	`//`
`// Revision 1.8 2002/02/14 20:54:33 billditt`	`// Revision 1.8 2002/02/14 20:54:33 billditt`
`// Addition of new module eth_addrcheck.v`	`// Addition of new module eth_addrcheck.v`
Line 275...	Line 278...
`reg LastByteIn;`	`reg LastByteIn;`
`reg ShiftWillEnd;`	`reg ShiftWillEnd;`

`reg WriteRxDataToFifo;`	`reg WriteRxDataToFifo;`
`reg [15:0] LatchedRxLength;`	`reg [15:0] LatchedRxLength;`
	`reg RxAbortLatched;`

`reg ShiftEnded;`	`reg ShiftEnded;`
`reg RxOverrun;`	`reg RxOverrun;`

`reg BDWrite; // BD Write Enable for access from WISHBONE side`	`reg BDWrite; // BD Write Enable for access from WISHBONE side`
Line 1674...	Line 1678...
`else`	`else`
`RxAbortSyncb2 <=#Tp RxAbortSyncb1;`	`RxAbortSyncb2 <=#Tp RxAbortSyncb1;`
`end`	`end`


	`always @ (posedge MRxClk or posedge Reset)`
	`begin`
	`if(Reset)`
	`RxAbortLatched <=#Tp 1'b0;`
	`else`
	`if(RxAbort)`
	`RxAbortLatched <=#Tp 1'b1;`
	`else`
	`if(RxStartFrm)`
	`RxAbortLatched <=#Tp 1'b0;`
	`end`





`// Interrupts`	`// Interrupts`
Line 1688...	Line 1704...
`assign Busy_IRQ = 1'b0;`	`assign Busy_IRQ = 1'b0;`



`reg LoadStatusBlocked;`	`reg LoadStatusBlocked;`

`always @ (posedge MRxClk or posedge Reset)`	`always @ (posedge MRxClk or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`LoadStatusBlocked <=#Tp 1'b0;`	`LoadStatusBlocked <=#Tp 1'b0;`
`else`	`else`
`if(LoadRxStatus)`	`if(LoadRxStatus & ~RxAbortLatched)`
`LoadStatusBlocked <=#Tp 1'b1;`	`LoadStatusBlocked <=#Tp 1'b1;`
`else`	`else`
`if(RxStatusWrite_rck)`	`if(RxStatusWrite_rck)`
`LoadStatusBlocked <=#Tp 1'b0;`	`LoadStatusBlocked <=#Tp 1'b0;`
`end`	`end`
Line 1706...	Line 1723...
`always @ (posedge MRxClk or posedge Reset)`	`always @ (posedge MRxClk or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`LatchedRxLength[15:0] <=#Tp 16'h0;`	`LatchedRxLength[15:0] <=#Tp 16'h0;`
`else`	`else`
`if(LoadRxStatus & ~LoadStatusBlocked)`	`if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)`
`LatchedRxLength[15:0] <=#Tp RxLength[15:0];`	`LatchedRxLength[15:0] <=#Tp RxLength[15:0];`
`end`	`end`


`assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};`	`assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};`
Line 1718...	Line 1735...
`always @ (posedge MRxClk or posedge Reset)`	`always @ (posedge MRxClk or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`RxStatusInLatched <=#Tp 'h0;`	`RxStatusInLatched <=#Tp 'h0;`
`else`	`else`
`if(LoadRxStatus & ~LoadStatusBlocked)`	`if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)`
`RxStatusInLatched <=#Tp RxStatusIn;`	`RxStatusInLatched <=#Tp RxStatusIn;`
`end`	`end`


`// Rx overrun`	`// Rx overrun`

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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 61 and 64