URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 82 and 86

Rev 82	Rev 86
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.14 2002/03/02 19:12:40 mohor`
	`// Byte ordering changed (Big Endian used). casex changed with case because`
	`// Xilinx Foundation had problems. Tested in HW. It WORKS.`
	`//`
`// Revision 1.13 2002/02/26 16:59:55 mohor`	`// Revision 1.13 2002/02/26 16:59:55 mohor`
`// Small fixes for external/internal DMA missmatches.`	`// Small fixes for external/internal DMA missmatches.`
`//`	`//`
`// Revision 1.12 2002/02/26 16:22:07 mohor`	`// Revision 1.12 2002/02/26 16:22:07 mohor`
`// Interrupts changed`	`// Interrupts changed`
Line 1127...	Line 1131...
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`TxData <=#Tp 8'h0;`	`TxData <=#Tp 8'h0;`
`else`	`else`
`if(TxStartFrm_sync2 & ~TxStartFrm)`	`if(TxStartFrm_sync2 & ~TxStartFrm)`
`TxData <=#Tp TxData_wb[7:0];`	`// TxData <=#Tp TxData_wb[7:0];`
	`TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering`
`else`	`else`
`if(TxUsedData & Flop)`	`if(TxUsedData & Flop)`
`begin`	`begin`
`case(TxByteCnt)`	`case(TxByteCnt)`
`// 0 : TxData <=#Tp TxDataLatched[7:0];`	`// 0 : TxData <=#Tp TxDataLatched[7:0];`