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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Unconnected signals are now connected.
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// Unconnected signals are now connected.
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//
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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Line 163... |
Line 173... |
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wire Write = Cs & Rw;
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wire Write = Cs & Rw;
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wire Read = Cs & ~Rw;
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wire Read = Cs & ~Rw;
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wire MODER_Wr = (Address == `MODER_ADR) & Write;
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wire MODER_Wr = (Address == `ETH_MODER_ADR) & Write;
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wire INT_SOURCE_Wr = (Address == `INT_SOURCE_ADR) & Write;
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wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR) & Write;
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wire INT_MASK_Wr = (Address == `INT_MASK_ADR) & Write;
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wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR) & Write;
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wire IPGT_Wr = (Address == `IPGT_ADR) & Write;
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wire IPGT_Wr = (Address == `ETH_IPGT_ADR) & Write;
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wire IPGR1_Wr = (Address == `IPGR1_ADR) & Write;
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wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR) & Write;
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wire IPGR2_Wr = (Address == `IPGR2_ADR) & Write;
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wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR) & Write;
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wire PACKETLEN_Wr = (Address == `PACKETLEN_ADR) & Write;
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wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR) & Write;
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wire COLLCONF_Wr = (Address == `COLLCONF_ADR) & Write;
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wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR) & Write;
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wire CTRLMODER_Wr = (Address == `CTRLMODER_ADR) & Write;
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wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR) & Write;
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wire MIIMODER_Wr = (Address == `MIIMODER_ADR) & Write;
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wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR) & Write;
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wire MIICOMMAND_Wr = (Address == `MIICOMMAND_ADR) & Write;
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wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR) & Write;
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wire MIIADDRESS_Wr = (Address == `MIIADDRESS_ADR) & Write;
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wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR) & Write;
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wire MIITX_DATA_Wr = (Address == `MIITX_DATA_ADR) & Write;
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wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR) & Write;
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wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
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wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
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wire MIISTATUS_Wr = (Address == `MIISTATUS_ADR) & Write;
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wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR) & Write;
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wire MAC_ADDR0_Wr = (Address == `MAC_ADDR0_ADR) & Write;
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wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR) & Write;
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wire MAC_ADDR1_Wr = (Address == `MAC_ADDR1_ADR) & Write;
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wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR) & Write;
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assign RX_BD_ADR_Wr = (Address == `RX_BD_ADR_ADR) & Write;
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assign RX_BD_ADR_Wr = (Address == `ETH_RX_BD_ADR_ADR) & Write;
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [31:0] INT_SOURCEOut;
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wire [31:0] INT_SOURCEOut;
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Line 214... |
wire [31:0] MIISTATUSOut;
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wire [31:0] MIISTATUSOut;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] RX_BD_ADROut;
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wire [31:0] RX_BD_ADROut;
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MODER_DEF));
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) INT_SOURCE (.DataIn(DataIn), .DataOut(INT_SOURCEOut), .Write(INT_SOURCE_Wr), .Clk(Clk), .Reset(Reset), .Default(`INT_SOURCE_DEF));
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eth_register #(32) INT_SOURCE (.DataIn(DataIn), .DataOut(INT_SOURCEOut), .Write(INT_SOURCE_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_SOURCE_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`INT_MASK_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`IPGT_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`IPGR1_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`IPGR2_DEF));
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eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`PACKETLEN_DEF));
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
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eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`COLLCONF_DEF));
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eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF));
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// CTRLMODER registers
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// CTRLMODER registers
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wire [31:0] DefaultCtrlModer = `CTRLMODER_DEF;
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wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF;
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assign CTRLMODEROut[31:3] = 29'h0;
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assign CTRLMODEROut[31:3] = 29'h0;
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eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
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eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
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// End: CTRLMODER registers
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// End: CTRLMODER registers
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eth_register #(32) MIIMODER (.DataIn(DataIn), .DataOut(MIIMODEROut), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIIMODER_DEF));
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eth_register #(32) MIIMODER (.DataIn(DataIn), .DataOut(MIIMODEROut), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
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assign MIICOMMANDOut[31:3] = 29'h0;
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assign MIICOMMANDOut[31:3] = 29'h0;
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eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
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eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
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eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
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eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
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eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
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eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
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eth_register #(32) MIIADDRESS (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIIADDRESS_DEF));
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eth_register #(32) MIIADDRESS (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF));
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eth_register #(32) MIITX_DATA (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIITX_DATA_DEF));
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eth_register #(32) MIITX_DATA (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
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eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIIRX_DATA_DEF));
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eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
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//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`MIISTATUS_DEF));
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//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF));
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eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`MAC_ADDR0_DEF));
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eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
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eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`MAC_ADDR1_DEF));
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eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
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assign RX_BD_ADROut[31:8] = 24'h0;
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assign RX_BD_ADROut[31:8] = 24'h0;
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eth_register #(8) RX_BD_ADR (.DataIn(DataIn[7:0]), .DataOut(RX_BD_ADROut[7:0]), .Write(RX_BD_ADR_Wr), .Clk(Clk), .Reset(Reset), .Default(`RX_BD_ADR_DEF));
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eth_register #(8) RX_BD_ADR (.DataIn(DataIn[7:0]), .DataOut(RX_BD_ADROut[7:0]), .Write(RX_BD_ADR_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_RX_BD_ADR_DEF));
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reg LinkFailRegister;
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reg LinkFailRegister;
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wire ResetLinkFailRegister = Address == `MIISTATUS_ADR & Read;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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reg ResetLinkFailRegister_q1;
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reg ResetLinkFailRegister_q1;
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reg ResetLinkFailRegister_q2;
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reg ResetLinkFailRegister_q2;
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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Line 275... |
Line 285... |
RX_BD_ADROut)
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RX_BD_ADROut)
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begin
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begin
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if(Read) // read
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if(Read) // read
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begin
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begin
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case(Address)
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case(Address)
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`MODER_ADR : DataOut<=MODEROut;
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`ETH_MODER_ADR : DataOut<=MODEROut;
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`INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
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`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
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`INT_MASK_ADR : DataOut<=INT_MASKOut;
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`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
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`IPGT_ADR : DataOut<=IPGTOut;
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`ETH_IPGT_ADR : DataOut<=IPGTOut;
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`IPGR1_ADR : DataOut<=IPGR1Out;
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`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
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`IPGR2_ADR : DataOut<=IPGR2Out;
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`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
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`PACKETLEN_ADR : DataOut<=PACKETLENOut;
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`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
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`COLLCONF_ADR : DataOut<=COLLCONFOut;
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`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
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`CTRLMODER_ADR : DataOut<=CTRLMODEROut;
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`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
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`MIIMODER_ADR : DataOut<=MIIMODEROut;
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`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
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`MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
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`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
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`MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
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`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
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`MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
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`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
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`MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
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`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
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`MIISTATUS_ADR : DataOut<=MIISTATUSOut;
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`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
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`MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
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`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
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`MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
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`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
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`RX_BD_ADR_ADR : DataOut<=RX_BD_ADROut;
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`ETH_RX_BD_ADR_ADR : DataOut<=RX_BD_ADROut;
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default: DataOut<=32'h0;
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default: DataOut<=32'h0;
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endcase
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endcase
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end
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end
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else
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else
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DataOut<=32'h0;
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DataOut<=32'h0;
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