Line 11... |
Line 11... |
//// All additional information is avaliable in the Readme.txt ////
|
//// All additional information is avaliable in the Readme.txt ////
|
//// file. ////
|
//// file. ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2001 Authors ////
|
//// Copyright (C) 2001, 2002 Authors ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.28 2002/07/18 16:11:46 mohor
|
|
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
|
|
//
|
// Revision 1.27 2002/07/11 02:53:20 mohor
|
// Revision 1.27 2002/07/11 02:53:20 mohor
|
// RxPointer bug fixed.
|
// RxPointer bug fixed.
|
//
|
//
|
// Revision 1.26 2002/07/10 13:12:38 mohor
|
// Revision 1.26 2002/07/10 13:12:38 mohor
|
// Previous bug wasn't succesfully removed. Now fixed.
|
// Previous bug wasn't succesfully removed. Now fixed.
|
Line 1626... |
Line 1629... |
end
|
end
|
|
|
reg ShiftEnded_tck;
|
reg ShiftEnded_tck;
|
reg ShiftEndedSync1;
|
reg ShiftEndedSync1;
|
reg ShiftEndedSync2;
|
reg ShiftEndedSync2;
|
|
reg ShiftEndedSync3;
|
|
reg ShiftEndedSync_c1;
|
|
reg ShiftEndedSync_c2;
|
|
|
wire StartShiftWillEnd;
|
wire StartShiftWillEnd;
|
//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
|
|
// Indicating that data reception will end
|
// Indicating that data reception will end
|
Line 1833... |
Line 1840... |
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
|
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk(WB_CLK_I), .reset(Reset),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.empty(RxBufferEmpty), .cnt()
|
.empty(RxBufferEmpty), .cnt()
|
);
|
);
|
|
|
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
|
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
|
|
|
Line 1847... |
Line 1854... |
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEnded_tck <=#Tp 1'b0;
|
ShiftEnded_tck <=#Tp 1'b0;
|
else
|
else
|
if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort & ~ShiftEnded_tck)
|
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
|
ShiftEnded_tck <=#Tp 1'b1;
|
ShiftEnded_tck <=#Tp 1'b1;
|
else
|
else
|
if(ShiftEnded | RxAbort)
|
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
|
ShiftEnded_tck <=#Tp 1'b0;
|
ShiftEnded_tck <=#Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
Line 1870... |
Line 1877... |
ShiftEndedSync2 <=#Tp 1'b0;
|
ShiftEndedSync2 <=#Tp 1'b0;
|
else
|
else
|
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
|
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
|
end
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftEndedSync3 <=#Tp 1'b0;
|
|
else
|
|
if(ShiftEndedSync1 & ~ShiftEndedSync2)
|
|
ShiftEndedSync3 <=#Tp 1'b1;
|
|
else
|
|
if(ShiftEnded)
|
|
ShiftEndedSync3 <=#Tp 1'b0;
|
|
end
|
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEnded <=#Tp 1'b0;
|
ShiftEnded <=#Tp 1'b0;
|
else
|
else
|
if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
|
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
|
ShiftEnded <=#Tp 1'b1;
|
ShiftEnded <=#Tp 1'b1;
|
else
|
else
|
if(RxStatusWrite)
|
if(RxStatusWrite)
|
ShiftEnded <=#Tp 1'b0;
|
ShiftEnded <=#Tp 1'b0;
|
end
|
end
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftEndedSync_c1 <=#Tp 1'b0;
|
|
else
|
|
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
|
|
end
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ShiftEndedSync_c2 <=#Tp 1'b0;
|
|
else
|
|
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
|
|
end
|
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|