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// specific elements.
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// specific elements.
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_MODER_ADR 6'h0 // 0x0
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_INT_MASK_ADR 6'h2 // 0x8
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`define ETH_IPGT_ADR 8'h3 // 0xC
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`define ETH_IPGT_ADR 6'h3 // 0xC
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`define ETH_IPGR1_ADR 8'h4 // 0x10
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`define ETH_IPGR1_ADR 6'h4 // 0x10
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`define ETH_IPGR2_ADR 8'h5 // 0x14
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`define ETH_IPGR2_ADR 6'h5 // 0x14
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`define ETH_PACKETLEN_ADR 8'h6 // 0x18
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`define ETH_PACKETLEN_ADR 6'h6 // 0x18
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`define ETH_COLLCONF_ADR 8'h7 // 0x1C
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`define ETH_COLLCONF_ADR 6'h7 // 0x1C
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`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
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`define ETH_TX_BD_NUM_ADR 6'h8 // 0x20
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`define ETH_CTRLMODER_ADR 8'h9 // 0x24
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`define ETH_CTRLMODER_ADR 6'h9 // 0x24
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`define ETH_MIIMODER_ADR 8'hA // 0x28
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`define ETH_MIIMODER_ADR 6'hA // 0x28
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`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
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`define ETH_MIICOMMAND_ADR 6'hB // 0x2C
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`define ETH_MIIADDRESS_ADR 8'hC // 0x30
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`define ETH_MIIADDRESS_ADR 6'hC // 0x30
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`define ETH_MIITX_DATA_ADR 8'hD // 0x34
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`define ETH_MIITX_DATA_ADR 6'hD // 0x34
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`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
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`define ETH_MIIRX_DATA_ADR 6'hE // 0x38
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`define ETH_MIISTATUS_ADR 8'hF // 0x3C
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`define ETH_MIISTATUS_ADR 6'hF // 0x3C
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`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
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`define ETH_MAC_ADDR0_ADR 6'h10 // 0x40
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`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
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`define ETH_MAC_ADDR1_ADR 6'h11 // 0x44
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`define ETH_HASH0_ADR 8'h12 // 0x48
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`define ETH_HASH0_ADR 6'h12 // 0x48
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`define ETH_HASH1_ADR 8'h13 // 0x4C
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`define ETH_HASH1_ADR 6'h13 // 0x4C
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`define ETH_MODER_DEF 32'h0000A800
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`define ETH_MODER_DEF 32'h0000A800
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`define ETH_INT_SOURCE_DEF 32'h00000000
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`define ETH_INT_SOURCE_DEF 32'h00000000
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`define ETH_INT_MASK_DEF 32'h00000000
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`define ETH_INT_MASK_DEF 32'h00000000
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`define ETH_MAC_ADDR0_DEF 32'h00000000
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`define ETH_MAC_ADDR0_DEF 32'h00000000
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`define ETH_MAC_ADDR1_DEF 32'h00000000
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`define ETH_MAC_ADDR1_DEF 32'h00000000
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`define ETH_HASH0_DEF 32'h00000000
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`define ETH_HASH0_DEF 32'h00000000
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`define ETH_HASH1_DEF 32'h00000000
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`define ETH_HASH1_DEF 32'h00000000
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`define ETH_TX_BD_NUM_DEF 8'h80
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`define ETH_TX_BD_NUM_DEF 8'h80
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// Outputs are registered (uncomment when needed)
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// Outputs are registered (uncomment when needed)
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// `define ETH_REGISTERED_OUTPUTS
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// `define ETH_REGISTERED_OUTPUTS
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`define RX_FIFO_CNT_WIDTH 4
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`define RX_FIFO_CNT_WIDTH 4
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`define RX_FIFO_DEPTH 8
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`define RX_FIFO_DEPTH 8
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`define RX_FIFO_DATA_WIDTH 32
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`define RX_FIFO_DATA_WIDTH 32
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No newline at end of file
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No newline at end of file
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`define MULTICAST_XFR 0
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`define UNICAST_XFR 1
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`define BROADCAST_XFR 2
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No newline at end of file
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No newline at end of file
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