| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2001/08/15 14:03:59 mohor
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|
// Signal names changed on the top level for easier pad insertion (ASIC).
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|
//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
|
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
|
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
|
// Include files fixed to contain no path.
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// Include files fixed to contain no path.
|
// File names and module names changed ta have a eth_ prologue in the name.
|
// File names and module names changed ta have a eth_ prologue in the name.
|
// File eth_timescale.v is used to define timescale
|
// File eth_timescale.v is used to define timescale
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| Line 58... |
Line 61... |
// Directory structure changed. Files checked and joind together.
|
// Directory structure changed. Files checked and joind together.
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//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
|
|
|
|
|
|
|
`include "eth_defines.v"
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`include "eth_defines.v"
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`include "eth_timescale.v"
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`include "eth_timescale.v"
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|
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| Line 76... |
Line 77... |
// WISHBONE slave
|
// WISHBONE slave
|
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
|
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
|
wb_req_o, wb_ack_i, wb_nd_o, wb_rd_o,
|
wb_req_o, wb_ack_i, wb_nd_o, wb_rd_o,
|
|
|
//TX
|
//TX
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mtxclk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
|
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
|
|
|
//RX
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//RX
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mrxclk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
|
|
|
// MIIM
|
// MIIM
|
mdc_pad_o, md_pad_i, md_pad_o, md_pad_oe
|
mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o
|
|
|
|
|
);
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);
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|
|
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| Line 113... |
Line 114... |
output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output wb_rd_o; // DMA restart descriptor output
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output wb_rd_o; // DMA restart descriptor output
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|
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// Tx
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// Tx
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input mtxclk_pad_i; // Transmit clock (from PHY)
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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output mtxerr_pad_o; // Transmit error (to PHY)
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output mtxerr_pad_o; // Transmit error (to PHY)
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|
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// Rx
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// Rx
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input mrxclk_pad_i; // Receive clock (from PHY)
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input mrx_clk_pad_i; // Receive clock (from PHY)
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input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
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input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
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input mrxdv_pad_i; // Receive data valid (from PHY)
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input mrxdv_pad_i; // Receive data valid (from PHY)
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input mrxerr_pad_i; // Receive data error (from PHY)
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input mrxerr_pad_i; // Receive data error (from PHY)
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|
|
// Common Tx and Rx
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// Common Tx and Rx
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| Line 132... |
Line 133... |
|
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// MII Management interface
|
// MII Management interface
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input md_pad_i; // MII data input (from I/O cell)
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input md_pad_i; // MII data input (from I/O cell)
|
output mdc_pad_o; // MII Management data clock (to PHY)
|
output mdc_pad_o; // MII Management data clock (to PHY)
|
output md_pad_o; // MII data output (to I/O cell)
|
output md_pad_o; // MII data output (to I/O cell)
|
output md_pad_oe; // MII data output enable (to I/O cell)
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output md_padoen_o; // MII data output enable (to I/O cell)
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|
|
|
|
wire [7:0] r_ClkDiv;
|
wire [7:0] r_ClkDiv;
|
wire r_MiiNoPre;
|
wire r_MiiNoPre;
|
wire [15:0] r_CtrlData;
|
wire [15:0] r_CtrlData;
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| Line 171... |
Line 172... |
(
|
(
|
.Clk(wb_clk_i), .Reset(r_MiiMRst), .Divider(r_ClkDiv),
|
.Clk(wb_clk_i), .Reset(r_MiiMRst), .Divider(r_ClkDiv),
|
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
|
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
|
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
|
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
|
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
|
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
|
.MdoEn(md_pad_oe), .Mdc(mdc_pad_o), .Busy(Busy_stat),
|
.MdoEn(md_padoen_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
|
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
|
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
|
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
|
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
|
);
|
);
|
|
|
|
|
| Line 225... |
Line 226... |
wire BDAck;
|
wire BDAck;
|
wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
|
wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
|
|
|
|
|
|
|
assign EthAddMatch = wb_adr_i[31:16] == `ETHERNET_SPACE;
|
assign EthAddMatch = wb_adr_i[31:16] == `ETH_ETHERNET_SPACE;
|
assign WB_STB_I_eth = wb_stb_i & EthAddMatch;
|
assign WB_STB_I_eth = wb_stb_i & EthAddMatch;
|
assign WB_CYC_I_eth = wb_stb_i & EthAddMatch;
|
assign WB_CYC_I_eth = wb_stb_i & EthAddMatch;
|
|
|
assign wb_err_o = wb_stb_i & wb_cyc_i & EthAddMatch & ~DWord;
|
assign wb_err_o = wb_stb_i & wb_cyc_i & EthAddMatch & ~DWord;
|
assign DWord = &wb_sel_i;
|
assign DWord = &wb_sel_i;
|
assign RegCs = wb_stb_i & wb_cyc_i & DWord & EthAddMatch & (wb_adr_i[15:12] == `REG_SPACE);
|
assign RegCs = wb_stb_i & wb_cyc_i & DWord & EthAddMatch & (wb_adr_i[15:12] == `ETH_REG_SPACE);
|
assign RegAck = RegCs;
|
assign RegAck = RegCs;
|
assign wb_ack_o = RegAck | BDAck;
|
assign wb_ack_o = RegAck | BDAck;
|
|
|
|
|
// Selecting the WISHBONE output data
|
// Selecting the WISHBONE output data
|
| Line 287... |
Line 288... |
wire ReceivedLengthOK;
|
wire ReceivedLengthOK;
|
|
|
// Connecting MACControl
|
// Connecting MACControl
|
eth_maccontrol maccontrol1
|
eth_maccontrol maccontrol1
|
(
|
(
|
.MTxClk(mtxclk_pad_i), .TPauseRq(TPauseRq),
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.TxPauseTV(TxPauseTV), .TxDataIn(TxData),
|
.TxPauseTV(TxPauseTV), .TxDataIn(TxData),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxAbortIn(TxAbortIn), .MRxClk(mrxclk_pad_i),
|
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
|
.RxData(RxData), .RxValid(RxValid),
|
.RxData(RxData), .RxValid(RxValid),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
|
.PassAll(r_PassAll), .TxFlow(r_TxFlow),
|
.PassAll(r_PassAll), .TxFlow(r_TxFlow),
|
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
|
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
|
| Line 340... |
Line 341... |
|
|
|
|
// Connecting TxEthMAC
|
// Connecting TxEthMAC
|
eth_txethmac txethmac1
|
eth_txethmac txethmac1
|
(
|
(
|
.MTxClk(mtxclk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense),
|
.MTxClk(mtx_clk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense),
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
|
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
|
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
|
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
|
| Line 372... |
Line 373... |
|
|
|
|
// Connecting RxEthMAC
|
// Connecting RxEthMAC
|
eth_rxethmac rxethmac1
|
eth_rxethmac rxethmac1
|
(
|
(
|
.MRxClk(mrxclk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
.RxEndFrm(RxEndFrm), .CrcHash(), .CrcHashGood(),
|
.RxEndFrm(RxEndFrm), .CrcHash(), .CrcHashGood(),
|
.Broadcast(), .Multicast(), .ByteCnt(RxByteCnt),
|
.Broadcast(), .Multicast(), .ByteCnt(RxByteCnt),
|
| Line 385... |
Line 386... |
.StateSFD(RxStateSFD), .StateData(RxStateData)
|
.StateSFD(RxStateSFD), .StateData(RxStateData)
|
);
|
);
|
|
|
|
|
// MII Carrier Sense Synchronization
|
// MII Carrier Sense Synchronization
|
always @ (posedge mtxclk_pad_i or posedge r_Rst)
|
always @ (posedge mtx_clk_pad_i or posedge r_Rst)
|
begin
|
begin
|
if(r_Rst)
|
if(r_Rst)
|
begin
|
begin
|
CarrierSense_Tx1 <= #Tp 1'b0;
|
CarrierSense_Tx1 <= #Tp 1'b0;
|
CarrierSense_Tx2 <= #Tp 1'b0;
|
CarrierSense_Tx2 <= #Tp 1'b0;
|
| Line 403... |
Line 404... |
|
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
|
|
|
|
|
// MII Collision Synchronization
|
// MII Collision Synchronization
|
always @ (posedge mtxclk_pad_i or posedge r_Rst)
|
always @ (posedge mtx_clk_pad_i or posedge r_Rst)
|
begin
|
begin
|
if(r_Rst)
|
if(r_Rst)
|
begin
|
begin
|
Collision_Tx1 <= #Tp 1'b0;
|
Collision_Tx1 <= #Tp 1'b0;
|
Collision_Tx2 <= #Tp 1'b0;
|
Collision_Tx2 <= #Tp 1'b0;
|
| Line 428... |
Line 429... |
assign Collision = ~r_FullD & Collision_Tx2;
|
assign Collision = ~r_FullD & Collision_Tx2;
|
|
|
|
|
|
|
// Carrier sense is synchronized to receive clock.
|
// Carrier sense is synchronized to receive clock.
|
always @ (posedge mrxclk_pad_i or posedge r_Rst)
|
always @ (posedge mrx_clk_pad_i or posedge r_Rst)
|
begin
|
begin
|
if(r_Rst)
|
if(r_Rst)
|
begin
|
begin
|
CarrierSense_Rx1 <= #Tp 1'h0;
|
CarrierSense_Rx1 <= #Tp 1'h0;
|
RxCarrierSense <= #Tp 1'h0;
|
RxCarrierSense <= #Tp 1'h0;
|
| Line 444... |
Line 445... |
end
|
end
|
end
|
end
|
|
|
|
|
// Delayed WillTransmit
|
// Delayed WillTransmit
|
always @ (posedge mrxclk_pad_i)
|
always @ (posedge mrx_clk_pad_i)
|
begin
|
begin
|
WillTransmit_q <= #Tp WillTransmit;
|
WillTransmit_q <= #Tp WillTransmit;
|
WillTransmit_q2 <= #Tp WillTransmit_q;
|
WillTransmit_q2 <= #Tp WillTransmit_q;
|
end
|
end
|
|
|
| Line 456... |
Line 457... |
assign Transmitting = ~r_FullD & WillTransmit_q2;
|
assign Transmitting = ~r_FullD & WillTransmit_q2;
|
|
|
|
|
|
|
// Synchronized Receive Enable
|
// Synchronized Receive Enable
|
always @ (posedge mrxclk_pad_i or posedge r_Rst)
|
always @ (posedge mrx_clk_pad_i or posedge r_Rst)
|
begin
|
begin
|
if(r_Rst)
|
if(r_Rst)
|
RxEnSync <= #Tp 1'b0;
|
RxEnSync <= #Tp 1'b0;
|
else
|
else
|
if(~RxCarrierSense | RxCarrierSense & Transmitting)
|
if(~RxCarrierSense | RxCarrierSense & Transmitting)
|
| Line 481... |
Line 482... |
.WB_CYC_I(WB_CYC_I_eth), .WB_STB_I(WB_STB_I_eth), .WB_ACK_O(BDAck),
|
.WB_CYC_I(WB_CYC_I_eth), .WB_STB_I(WB_STB_I_eth), .WB_ACK_O(BDAck),
|
.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
|
.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
|
.WB_RD_O(wb_rd_o),
|
.WB_RD_O(wb_rd_o),
|
|
|
//TX
|
//TX
|
.MTxClk(mtxclk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0),
|
.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),
|
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),
|
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame),
|
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame),
|
.TxCtrlEndFrm(TxCtrlEndFrm),
|
.TxCtrlEndFrm(TxCtrlEndFrm),
|
| Line 493... |
Line 494... |
// Register
|
// Register
|
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDAddress(r_RxBDAddress),
|
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDAddress(r_RxBDAddress),
|
.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr),
|
.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr),
|
|
|
//RX
|
//RX
|
.MRxClk(mrxclk_pad_i), .RxData(RxData), .RxValid(RxValid),
|
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm)
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm)
|
);
|
);
|
|
|
|
|
|
|
// Connecting MacStatus module
|
// Connecting MacStatus module
|
eth_macstatus macstatus1
|
eth_macstatus macstatus1
|
(
|
(
|
.MRxClk(mrxclk_pad_i), .Reset(r_Rst), .TransmitEnd(),
|
.MRxClk(mrx_clk_pad_i), .Reset(r_Rst), .TransmitEnd(),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
|
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
|
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
|
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
|
