Line 1... |
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Please use tb_ethernet.v for testbench. Testbench will soon be
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updated.
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tb_eth_top.v ////
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//// tb_eth_top.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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Line 39... |
Line 62... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2002/05/03 10:25:01 mohor
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// Testbench supports unaligned accesses.
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//
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// Revision 1.12 2002/02/26 17:01:09 mohor
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// Revision 1.12 2002/02/26 17:01:09 mohor
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// Small fixes for external/internal DMA missmatches.
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// Small fixes for external/internal DMA missmatches.
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//
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//
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// Revision 1.11 2002/02/16 13:06:59 mohor
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// Revision 1.11 2002/02/16 13:06:59 mohor
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// EXTERNAL_DMA used instead of WISHBONE_DMA.
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// EXTERNAL_DMA used instead of WISHBONE_DMA.
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Line 121... |
Line 147... |
wire [31:0] WB_DAT_O;
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wire [31:0] WB_DAT_O;
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wire WB_ACK_O;
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wire WB_ACK_O;
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wire WB_ERR_O;
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wire WB_ERR_O;
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reg [1:0] WB_ACK_I;
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reg [1:0] WB_ACK_I;
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`ifdef EXTERNAL_DMA
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wire [1:0] WB_REQ_O;
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wire [1:0] WB_ND_O;
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wire WB_RD_O;
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`else
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// WISHBONE master
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// WISHBONE master
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wire [31:0] m_wb_adr_o;
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wire [31:0] m_wb_adr_o;
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wire [3:0] m_wb_sel_o;
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wire [3:0] m_wb_sel_o;
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wire m_wb_we_o;
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wire m_wb_we_o;
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reg [31:0] m_wb_dat_i;
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reg [31:0] m_wb_dat_i;
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wire [31:0] m_wb_dat_o;
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wire [31:0] m_wb_dat_o;
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wire m_wb_cyc_o;
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wire m_wb_cyc_o;
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wire m_wb_stb_o;
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wire m_wb_stb_o;
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reg m_wb_ack_i;
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reg m_wb_ack_i;
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reg m_wb_err_i;
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reg m_wb_err_i;
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`endif
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reg MTxClk;
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reg MTxClk;
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wire [3:0] MTxD;
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wire [3:0] MTxD;
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wire MTxEn;
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wire MTxEn;
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wire MTxErr;
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wire MTxErr;
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Line 168... |
Line 188... |
reg [9:0] TxBDIndex;
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reg [9:0] TxBDIndex;
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reg [9:0] RxBDIndex;
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reg [9:0] RxBDIndex;
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reg LogEnable;
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reg LogEnable;
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`ifdef EXTERNAL_DMA
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`else
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integer mcd1;
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integer mcd1;
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integer mcd2;
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integer mcd2;
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`endif
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reg [5:0] g_last_txbd;
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// Connecting Ethernet top module
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// Connecting Ethernet top module
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eth_top ethtop
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eth_top ethtop
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(
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(
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Line 185... |
Line 204... |
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// WISHBONE slave
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// WISHBONE slave
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.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
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.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
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.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O),
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.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O),
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`ifdef EXTERNAL_DMA
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.wb_ack_i(WB_ACK_I), .wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),
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`else
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// WISHBONE master
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// WISHBONE master
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
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.m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
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.m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
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.m_wb_err_i(m_wb_err_i),
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.m_wb_err_i(m_wb_err_i),
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`endif
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//TX
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.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
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//RX
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.mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
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.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
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// MIIM
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.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
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.int_o()
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);
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bench_cop i_bench_cop
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(
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// WISHBONE common
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.wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
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// WISHBONE slave
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.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
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.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O),
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// WISHBONE master
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
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.m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
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.m_wb_err_i(m_wb_err_i),
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//TX
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//TX
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.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
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.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
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//RX
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//RX
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Line 223... |
Line 266... |
WB_SEL_I = 4'h0;
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WB_SEL_I = 4'h0;
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WB_WE_I = 1'b0;
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WB_WE_I = 1'b0;
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WB_CYC_I = 1'b0;
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WB_CYC_I = 1'b0;
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WB_STB_I = 1'b0;
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WB_STB_I = 1'b0;
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`ifdef EXTERNAL_DMA
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WB_ACK_I = 2'h0;
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`else
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m_wb_ack_i = 0;
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m_wb_ack_i = 0;
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m_wb_err_i = 0;
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m_wb_err_i = 0;
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`endif
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MTxClk = 1'b0;
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MTxClk = 1'b0;
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MRxClk = 1'b0;
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MRxClk = 1'b0;
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MRxD = 4'h0;
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MRxD = 4'h0;
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MRxDV = 1'b0;
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MRxDV = 1'b0;
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MRxErr = 1'b0;
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MRxErr = 1'b0;
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Line 242... |
Line 281... |
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WishboneBusy = 1'b0;
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WishboneBusy = 1'b0;
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TxBDIndex = 10'h0;
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TxBDIndex = 10'h0;
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RxBDIndex = 10'h0;
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RxBDIndex = 10'h0;
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LogEnable = 1'b1;
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LogEnable = 1'b1;
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g_last_txbd = 6'h0;
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end
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end
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// Reset pulse
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// Reset pulse
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initial
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initial
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begin
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begin
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`ifdef EXTERNAL_DMA
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`else
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mcd1 = $fopen("ethernet_tx.log");
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mcd1 = $fopen("ethernet_tx.log");
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mcd2 = $fopen("ethernet_rx.log");
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mcd2 = $fopen("ethernet_rx.log");
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`endif
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WB_RST_I = 1'b1;
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WB_RST_I = 1'b1;
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#100 WB_RST_I = 1'b0;
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#100 WB_RST_I = 1'b0;
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#100 StartTB = 1'b1;
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#100 StartTB = 1'b1;
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end
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end
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Line 266... |
Line 303... |
always
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always
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begin
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begin
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// forever #2.5 WB_CLK_I = ~WB_CLK_I; // 2*2.5 ns -> 200.0 MHz
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// forever #2.5 WB_CLK_I = ~WB_CLK_I; // 2*2.5 ns -> 200.0 MHz
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// forever #5 WB_CLK_I = ~WB_CLK_I; // 2*5 ns -> 100.0 MHz
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// forever #5 WB_CLK_I = ~WB_CLK_I; // 2*5 ns -> 100.0 MHz
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// forever #10 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 50.0 MHz
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// forever #10 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 50.0 MHz
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forever #12.5 WB_CLK_I = ~WB_CLK_I; // 2*12.5 ns -> 40 MHz
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// forever #15 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 33.3 MHz
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// forever #15 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 33.3 MHz
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forever #18 WB_CLK_I = ~WB_CLK_I; // 2*18 ns -> 27.7 MHz
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// forever #20 WB_CLK_I = ~WB_CLK_I; // 2*20 ns -> 25 MHz
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// forever #25 WB_CLK_I = ~WB_CLK_I; // 2*25 ns -> 20.0 MHz
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// forever #25 WB_CLK_I = ~WB_CLK_I; // 2*25 ns -> 20.0 MHz
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// forever #31.25 WB_CLK_I = ~WB_CLK_I; // 2*31.25 ns -> 16.0 MHz
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// forever #31.25 WB_CLK_I = ~WB_CLK_I; // 2*31.25 ns -> 16.0 MHz
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// forever #50 WB_CLK_I = ~WB_CLK_I; // 2*50 ns -> 10.0 MHz
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// forever #50 WB_CLK_I = ~WB_CLK_I; // 2*50 ns -> 10.0 MHz
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// forever #55 WB_CLK_I = ~WB_CLK_I; // 2*55 ns -> 9.1 MHz
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// forever #55 WB_CLK_I = ~WB_CLK_I; // 2*55 ns -> 9.1 MHz
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end
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end
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Line 285... |
Line 323... |
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// Generating MRxClk clock
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// Generating MRxClk clock
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always
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always
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begin
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begin
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// #16 forever #20 MRxClk = ~MRxClk; // 2*20 ns -> 25 MHz
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// #16 forever #20 MRxClk = ~MRxClk; // 2*20 ns -> 25 MHz
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// #16 forever #200 MRxClk = ~MRxClk; // 2*200 ns -> 2.5 MHz
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#16 forever #200 MRxClk = ~MRxClk; // 2*200 ns -> 2.5 MHz
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#16 forever #62.5 MRxClk = ~MRxClk; // 2*62.5 ns -> 8 MHz // just for testing purposes
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// #16 forever #62.5 MRxClk = ~MRxClk; // 2*62.5 ns -> 8 MHz // just for testing purposes
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end
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`ifdef EXTERNAL_DMA
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initial
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begin
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wait(StartTB); // Start of testbench
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WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
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WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
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WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
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WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
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WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
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SendPacket(16'h0015, 1'b0);
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SendPacket(16'h0043, 1'b1); // Control frame
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SendPacket(16'h0025, 1'b0);
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SendPacket(16'h0045, 1'b0);
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SendPacket(16'h0025, 1'b0);
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ReceivePacket(16'h0012, 1'b1); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
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ReceivePacket(16'h0011, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
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WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register
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WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register
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#10000 $stop;
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end
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task WishboneWrite;
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input [31:0] Data;
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input [31:0] Address;
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integer ii;
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begin
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wait (~WishboneBusy);
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WishboneBusy = 1;
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@ (posedge WB_CLK_I);
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#1;
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WB_ADR_I = Address;
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WB_DAT_I = Data;
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WB_WE_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_STB_I = 1'b1;
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WB_SEL_I = 4'hf;
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wait(WB_ACK_O); // waiting for acknowledge response
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// Writing information about the access to the screen
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@ (posedge WB_CLK_I);
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if(~Address[11] & ~Address[10])
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$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
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else
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if(~Address[11] & Address[10])
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if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
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begin
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$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
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if(Data[9])
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$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
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end
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else
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$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
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else
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$write("\nWB write ?????????????? Data: 0x%x Addr: 0x%0x", Data, Address);
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#1;
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WB_ADR_I = 32'hx;
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WB_DAT_I = 32'hx;
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WB_WE_I = 1'bx;
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WB_CYC_I = 1'b0;
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WB_STB_I = 1'b0;
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WB_SEL_I = 4'hx;
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#5 WishboneBusy = 0;
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end
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endtask
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task WishboneRead;
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input [31:0] Address;
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reg [31:0] Data;
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integer ii;
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begin
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wait (~WishboneBusy);
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WishboneBusy = 1;
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@ (posedge WB_CLK_I);
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#1;
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WB_ADR_I = Address;
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WB_WE_I = 1'b0;
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WB_CYC_I = 1'b1;
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WB_STB_I = 1'b1;
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WB_SEL_I = 4'hf;
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for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
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begin
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@ (posedge WB_CLK_I);
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Data = WB_DAT_O;
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end
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if(ii==20)
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begin
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$display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
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Address, $time);
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#50 $stop;
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end
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@ (posedge WB_CLK_I);
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if(~Address[11] & ~Address[10])
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$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
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else
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if(~Address[11] & Address[10])
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if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
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begin
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$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
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end
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else
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$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
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else
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$write("\nWB read ????????? Data: 0x%x Addr: 0x%0x", Data, Address);
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#1;
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WB_ADR_I = 32'hx;
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WB_WE_I = 1'bx;
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WB_CYC_I = 1'b0;
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WB_STB_I = 1'b0;
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WB_SEL_I = 4'hx;
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#5 WishboneBusy = 0;
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end
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endtask
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task SendPacket;
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input [15:0] Length;
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input ControlFrame;
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reg Wrap;
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reg [31:0] TempAddr;
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reg [31:0] TempData;
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begin
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if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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Wrap = 1'b1;
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else
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Wrap = 1'b0;
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TempAddr = {22'h01, (TxBDIndex<<2)};
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TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
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#1;
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if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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TxBDIndex = 0;
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else
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TxBDIndex = TxBDIndex + 1;
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fork
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begin
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WishboneWrite(TempData, TempAddr); // Writing status to TxBD
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end
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begin
|
|
if(~ControlFrame)
|
|
WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
|
|
end
|
end
|
join
|
|
end
|
|
endtask
|
|
|
|
|
|
|
|
task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
input [15:0] LengthRx;
|
|
input RxControlFrame;
|
|
reg WrapRx;
|
|
reg [31:0] TempRxAddr;
|
|
reg [31:0] TempRxData;
|
|
reg abc;
|
|
begin
|
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
|
WrapRx = 1'b1;
|
|
else
|
|
WrapRx = 1'b0;
|
|
|
|
TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
|
|
|
|
TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
|
|
|
|
#1;
|
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
|
RxBDIndex = 0;
|
|
else
|
|
RxBDIndex = RxBDIndex + 1;
|
|
|
|
abc=1;
|
|
WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
|
|
abc=0;
|
|
fork
|
|
begin
|
|
#200;
|
|
if(RxControlFrame)
|
|
GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
|
|
else
|
|
GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
|
|
end
|
|
|
|
begin
|
|
if(RxControlFrame)
|
|
WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
|
|
else
|
|
WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
|
|
end
|
|
join
|
|
end
|
|
endtask
|
|
|
|
|
|
|
|
task WaitingForTxDMARequest;
|
|
input [3:0] Delay;
|
|
input [15:0] DMALength;
|
|
integer pp;
|
|
reg [7:0]a, b, c, d;
|
|
|
|
for(pp=0; pp*4<DMALength; pp=pp+1)
|
|
begin
|
|
a = 4*pp[7:0]+3;
|
|
b = 4*pp[7:0]+2;
|
|
c = 4*pp[7:0]+1;
|
|
d = 4*pp[7:0] ;
|
|
@ (posedge WB_REQ_O[0]);
|
|
repeat(Delay) @(posedge WB_CLK_I);
|
|
|
|
wait (~WishboneBusy);
|
|
WishboneBusy = 1;
|
|
#1;
|
|
WB_DAT_I = {a, b, c, d};
|
|
WB_ADR_I = {22'h02, pp[9:0]};
|
|
$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
|
|
|
|
WB_WE_I = 1'b1;
|
|
WB_CYC_I = 1'b1;
|
|
WB_STB_I = 1'b1;
|
|
WB_SEL_I = 4'hf;
|
|
WB_ACK_I[0] = 1'b1;
|
|
|
|
@ (posedge WB_CLK_I);
|
|
#1;
|
|
WB_ADR_I = 32'hx;
|
|
WB_DAT_I = 32'hx;
|
|
WB_WE_I = 1'bx;
|
|
WB_CYC_I = 1'b0;
|
|
WB_STB_I = 1'b0;
|
|
WB_SEL_I = 4'hx;
|
|
WB_ACK_I[0] = 1'b0;
|
|
#5 WishboneBusy = 0;
|
|
end
|
|
endtask
|
|
|
|
|
|
task WaitingForRxDMARequest;
|
|
input [3:0] Delay;
|
|
input [15:0] DMALengthRx;
|
|
integer rr;
|
|
|
|
for(rr=0; rr*4<DMALengthRx; rr=rr+1)
|
|
begin
|
|
@ (posedge WB_REQ_O[1]);
|
|
repeat(Delay) @(posedge WB_CLK_I);
|
|
|
|
wait (~WishboneBusy);
|
|
WishboneBusy = 1;
|
|
#1;
|
|
WB_ADR_I = {22'h02, rr[9:0]};
|
|
$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
|
|
|
|
WB_WE_I = 1'b1;
|
|
WB_CYC_I = 1'b1;
|
|
WB_STB_I = 1'b1;
|
|
WB_SEL_I = 4'hf;
|
|
WB_ACK_I[1] = 1'b1;
|
|
|
|
@ (posedge WB_CLK_I);
|
|
#1;
|
|
WB_ADR_I = 32'hx;
|
|
WB_WE_I = 1'bx;
|
|
WB_CYC_I = 1'b0;
|
|
WB_STB_I = 1'b0;
|
|
WB_SEL_I = 4'hx;
|
|
WB_ACK_I[1] = 1'b0;
|
|
#5 WishboneBusy = 0;
|
|
end
|
|
endtask
|
|
|
|
|
|
|
|
task GetDataOnMRxD;
|
|
input [15:0] Len;
|
|
integer tt;
|
|
|
|
begin
|
|
@ (posedge MRxClk);
|
|
MRxDV=1'b1;
|
|
|
|
for(tt=0; tt<15; tt=tt+1)
|
|
begin
|
|
MRxD=4'h5; // preamble
|
|
@ (posedge MRxClk);
|
|
end
|
|
MRxD=4'hd; // SFD
|
|
|
|
for(tt=0; tt<Len; tt=tt+1)
|
|
begin
|
|
@ (posedge MRxClk);
|
|
MRxD=tt[3:0];
|
|
@ (posedge MRxClk);
|
|
MRxD=tt[7:4];
|
|
end
|
|
@ (posedge MRxClk);
|
|
MRxDV=1'b0;
|
|
end
|
|
endtask
|
|
|
|
|
|
task GetControlDataOnMRxD;
|
|
input [15:0] Timer;
|
|
reg [127:0] Packet;
|
|
reg [127:0] Data;
|
|
reg [31:0] Crc;
|
|
integer tt;
|
|
|
|
begin
|
|
Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
|
|
Crc = 32'h6014fe08; // not a correct value
|
|
|
|
@ (posedge MRxClk);
|
|
MRxDV=1'b1;
|
|
|
|
for(tt=0; tt<15; tt=tt+1)
|
|
begin
|
|
MRxD=4'h5; // preamble
|
|
@ (posedge MRxClk);
|
|
end
|
|
MRxD=4'hd; // SFD
|
|
|
|
for(tt=0; tt<32; tt=tt+1)
|
|
begin
|
|
Data = Packet << (tt*4);
|
|
@ (posedge MRxClk);
|
|
MRxD=Data[127:124];
|
|
end
|
|
|
|
for(tt=0; tt<2; tt=tt+1) // timer
|
|
begin
|
|
Data[15:0] = Timer << (tt*8);
|
|
@ (posedge MRxClk);
|
|
MRxD=Data[11:8];
|
|
@ (posedge MRxClk);
|
|
MRxD=Data[15:12];
|
|
end
|
|
|
|
for(tt=0; tt<42; tt=tt+1) // padding
|
|
begin
|
|
Data[7:0] = 8'h0;
|
|
@ (posedge MRxClk);
|
|
MRxD=Data[3:0];
|
|
@ (posedge MRxClk);
|
|
MRxD=Data[3:0];
|
|
end
|
|
|
|
for(tt=0; tt<4; tt=tt+1) // crc
|
|
begin
|
|
Data[31:0] = Crc << (tt*8);
|
|
@ (posedge MRxClk);
|
|
MRxD=Data[27:24];
|
|
@ (posedge MRxClk);
|
|
MRxD=Data[31:28];
|
|
end
|
|
|
|
|
|
|
|
@ (posedge MRxClk);
|
|
MRxDV=1'b0;
|
|
end
|
|
endtask
|
|
|
|
`else // No EXTERNAL_DMA
|
|
|
|
initial
|
initial
|
begin
|
begin
|
wait(StartTB); // Start of testbench
|
wait(StartTB); // Start of testbench
|
|
|
// Reset eth MAC core
|
// Reset eth MAC core
|
Line 703... |
Line 339... |
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
|
|
|
InitializeMemory;
|
InitializeMemory;
|
|
|
// Select which test you want to run:
|
// Select which test you want to run:
|
TestTxAndRx;
|
// TestTxAndRx;
|
|
TestFullDuplex;
|
// TestUnicast;
|
// TestUnicast;
|
// TestBroadcast;
|
// TestBroadcast;
|
// TestMulticast;
|
// TestMulticast;
|
end
|
end
|
|
|
Line 742... |
Line 379... |
|
|
|
|
|
|
for(jj=0; jj<8; jj=jj+4)
|
for(jj=0; jj<8; jj=jj+4)
|
begin
|
begin
|
WishboneWriteData(`TX_BUF_BASE + jj, 32'hffffffff, 4'hf); // Initializing data to ff
|
WishboneWriteData(`TX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
|
end
|
end
|
|
|
for(jj=0; jj<8; jj=jj+4)
|
for(jj=0; jj<8; jj=jj+4)
|
begin
|
begin
|
WishboneWriteData(`RX_BUF_BASE + jj, 32'hffffffff, 4'hf); // Initializing data to ff
|
WishboneWriteData(`RX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
|
end
|
end
|
|
|
// SendPacketX(16'h0064, 1'b0, 2'h3);
|
// SendPacketX(16'h0064, 1'b0, 2'h3);
|
// SendPacketX(16'h0064, 1'b0, 2'h2);
|
// SendPacketX(16'h0064, 1'b0, 2'h2);
|
// SendPacketX(16'h0064, 1'b0, 2'h1);
|
// SendPacketX(16'h0064, 1'b0, 2'h1);
|
Line 760... |
Line 397... |
// SendPacket(16'h0011, 1'b0);
|
// SendPacket(16'h0011, 1'b0);
|
// SendPacket(16'h0012, 1'b0);
|
// SendPacket(16'h0012, 1'b0);
|
|
|
fork
|
fork
|
begin
|
begin
|
SendPacketX(16'h264, 1'b0, 2'h3);
|
/*
|
SendPacketX(16'h64, 1'b0, 2'h3);
|
SendPacketX(16'h0064, 1'b0, 2'h1);
|
|
SendPacketX(16'h0064, 1'b0, 2'h2);
|
|
SendPacketX(16'h0064, 1'b0, 2'h3);
|
|
SendPacketX(16'h0064, 1'b0, 2'h0);
|
|
*/
|
|
// SendPacketX(16'h264, 1'b0, 2'h3);
|
|
// SendPacketX(16'h64, 1'b0, 2'h3);
|
|
// SendPacketX(16'h104, 1'b0, 2'h3);
|
end
|
end
|
|
|
begin
|
begin
|
ReceivePacketX(16'h0030, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacketX(16'h0035, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacketX(16'h0040, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacketX(16'h0040, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacketX(16'h0035, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacketX(16'h0041, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacketX(16'h0062, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacketX(16'h0042, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
end
|
ReceivePacketX(16'h0043, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
join
|
ReceivePacketX(16'h0044, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
end
|
fork
|
|
begin
|
// begin
|
wait(tb_eth_top.ethtop.wishbone.TxStatusWrite); // wait until tx status is written
|
// for(ii=0; ii<10000; ii=ii+1)
|
end
|
// begin
|
|
// WishboneRead({22'h01, 10'b0}, data_in); // read back
|
|
// #100;
|
|
// end
|
|
// end
|
|
//join
|
|
|
|
//fork
|
|
/*
|
|
begin
|
|
repeat(4)
|
|
begin
|
|
wait(tb_eth_top.ethtop.wishbone.TxStatusWrite); // wait until tx status is written
|
|
@ (posedge WB_CLK_I)
|
|
#1;
|
|
end
|
|
end
|
|
*/
|
begin
|
begin
|
wait(tb_eth_top.ethtop.wishbone.RxStatusWrite); // wait until rx status is written
|
wait(tb_eth_top.ethtop.wishbone.RxStatusWrite); // wait until rx status is written
|
end
|
end
|
|
|
join
|
join
|
|
|
|
|
/*
|
/*
|
SendPacket(16'h0013, 1'b0);
|
SendPacket(16'h0013, 1'b0);
|
Line 872... |
Line 531... |
#100000 $stop;
|
#100000 $stop;
|
end
|
end
|
endtask //TestTxAndRx
|
endtask //TestTxAndRx
|
|
|
|
|
|
|
|
|
|
|
|
task TestFullDuplex;
|
|
|
|
integer ii, jj;
|
|
integer data_in, bd, pointer;
|
|
integer addr;
|
|
|
|
begin
|
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
|
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
|
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
|
|
|
|
WishboneWrite(32'h0000a40b, {26'h0, `ETH_MODER_ADR<<2}); // CrcEn, Pad en, full duplex, reject broadcast, RxEn, TxEn
|
|
|
|
WishboneWrite(32'h00000002, {26'h0, `ETH_MAC_ADDR1_ADR<<2}); // MAC = 000203040506
|
|
WishboneWrite(32'h03040506, {26'h0, `ETH_MAC_ADDR0_ADR<<2});
|
|
|
|
initialize_txbd(5);
|
|
initialize_rxbd(6);
|
|
|
|
send_packet(48'h000123456789, 16'h0064);
|
|
|
|
|
|
/*
|
|
for(ii=0; ii<12; ii=ii+1) begin
|
|
addr = 32'h400 + ii*4;
|
|
WishboneRead(addr, data_in);
|
|
$display("\n(%0t)\t\tRead TxBD %0x = 0x%x", $time, ii, data_in);
|
|
end
|
|
|
|
for(ii=0; ii<14; ii=ii+1) begin
|
|
addr = 32'h600 + ii*4;
|
|
WishboneRead(addr, data_in);
|
|
$display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, ii, data_in);
|
|
end
|
|
*/
|
|
|
|
// WishboneRead({22'h01, 10'b0}, data_in); // read back
|
|
// WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2)<<2)}, bd); // Read from TxBD
|
|
|
|
/*
|
|
for(jj=0; jj<8; jj=jj+4)
|
|
WishboneWriteData(`TX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
|
|
|
|
for(jj=0; jj<8; jj=jj+4)
|
|
WishboneWriteData(`RX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
|
|
|
|
|
|
fork
|
|
begin
|
|
SendPacketX(16'h0064, 1'b0, 2'h1);
|
|
SendPacketX(16'h0065, 1'b0, 2'h2);
|
|
SendPacketX(16'h0066, 1'b0, 2'h3);
|
|
SendPacketX(16'h0067, 1'b0, 2'h0);
|
|
end
|
|
|
|
begin
|
|
ReceivePacketX(16'h0040, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacketX(16'h0041, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacketX(16'h0042, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacketX(16'h0043, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacketX(16'h0044, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
end
|
|
*/
|
|
|
|
//fork
|
|
/*
|
|
begin
|
|
repeat(4)
|
|
begin
|
|
wait(tb_eth_top.ethtop.wishbone.TxStatusWrite); // wait until tx status is written
|
|
@ (posedge WB_CLK_I)
|
|
#1;
|
|
end
|
|
end
|
|
*/
|
|
|
|
/*
|
|
begin
|
|
wait(tb_eth_top.ethtop.wishbone.RxStatusWrite); // wait until rx status is written
|
|
end
|
|
|
|
join
|
|
*/
|
|
|
|
/*
|
|
SendPacket(16'h0013, 1'b0);
|
|
SendPacket(16'h0014, 1'b0);
|
|
|
|
SendPacket(16'h0030, 1'b0);
|
|
SendPacket(16'h0031, 1'b0);
|
|
SendPacket(16'h0032, 1'b0);
|
|
SendPacket(16'h0033, 1'b0);
|
|
SendPacket(16'h0025, 1'b0);
|
|
SendPacket(16'h0045, 1'b0);
|
|
SendPacket(16'h0025, 1'b0);
|
|
SendPacket(16'h0017, 1'b0);
|
|
*/
|
|
|
|
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h3); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h2); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h1); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
|
|
// ReceivePacket(16'h0050, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
// ReceivePacket(16'h0051, 1'b0, `UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
// ReceivePacket(16'h0052, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
// ReceivePacket(16'h0053, 1'b0, `BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
// ReceivePacket(16'h0054, 1'b0, `UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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// ReceivePacket(16'h0055, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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// ReceivePacket(16'h0056, 1'b0, `UNICAST_WRONG_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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repeat(1000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
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// WishboneRead({24'h04, (8'h0<<2)}, RxBD); // Read from TxBD register
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// WishboneRead({24'h04, (8'h1<<2)}, RxBD); // Read from TxBD register
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// WishboneRead({24'h04, (8'h2<<2)}, RxBD); // Read from TxBD register
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// WishboneRead({24'h04, (8'h3<<2)}, RxBD); // Read from TxBD register
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// WishboneRead({24'h04, (8'h4<<2)}, RxBD); // Read from TxBD register
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/*
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for(jj=0; jj<3; jj=jj+1) // How many TxBD do we want to read?
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begin
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WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2)<<2)}, bd); // Read from TxBD
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$display("\n(%0t)\t\tRead TxBD %0x = 0x%x", $time, jj, bd);
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if(~bd[15]) // Ready = 0?
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begin
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WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2+1'h1)<<2)}, pointer); // Read TxBD pointer
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$display("\t\t\tRead TxBDPointer 0x=%x", pointer);
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$write("\t\t\tData:");
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for(ii=0; ii<bd[31:16]; ii=ii+4)
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begin
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WishboneReadData({pointer[31:2], 2'h0}+ii, data_in); // Read data from Tx Pointer
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$write("\t0x%x", data_in);
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end
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end
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end
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for(jj=0; jj<3; jj=jj+1) // How many RxBD do we want to read?
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begin
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WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2)<<2)}, bd); // Read from RxBD
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$display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, jj, bd);
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if(~bd[15]) // Empty = 0?
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begin
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WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2+1'h1)<<2)}, pointer); // Read RxBD pointer
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$display("\t\t\tRead RxBDPointer 0x=%x", pointer);
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$write("\t\t\tData:");
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for(ii=0; ii<bd[31:16]+4; ii=ii+4)
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begin
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WishboneReadData({pointer[31:2], 2'h0} + ii, data_in); // Read data from Rx Pointer
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$write("\t0x%x", data_in);
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end
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end
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end
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WishboneRead({22'h01, (10'h81<<2)}, data_in); // Read from RxBD register
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WishboneRead({22'h01, (10'h82<<2)}, data_in); // Read from RxBD register
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WishboneRead({22'h01, (10'h83<<2)}, data_in); // Read from RxBD register
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WishboneRead({22'h01, (10'h84<<2)}, data_in); // Read from RxBD register
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WishboneRead({22'h01, (10'h85<<2)}, data_in); // Read from RxBD register
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WishboneRead({22'h01, (10'h86<<2)}, data_in); // Read from RxBD register
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WishboneRead({22'h01, (10'h87<<2)}, data_in); // Read from RxBD register
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*/
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#100000 $stop;
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end
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endtask //TestFullDuplex
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task initialize_txbd;
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input [6:0] txbd_num;
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integer i, j;
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integer bd_status_addr, buf_addr, bd_ptr_addr;
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for(i=0; i<txbd_num; i=i+1) begin
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buf_addr = `TX_BUF_BASE + i * 32'h600;
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bd_status_addr = `TX_BD_BASE + i * 8;
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bd_ptr_addr = bd_status_addr + 4;
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// Initializing BD - status
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if(i==txbd_num-1)
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WishboneWrite(32'h00007800, bd_status_addr); // last BD: + WRAP
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else
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WishboneWrite(32'h00005800, bd_status_addr); // IRQ + PAD + CRC
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WishboneWrite(buf_addr, bd_ptr_addr); // Initializing BD - pointer
|
|
end
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endtask // initialize_txbd
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task initialize_rxbd;
|
|
input [6:0] rxbd_num;
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|
|
integer i, j;
|
|
integer bd_status_addr, buf_addr, bd_ptr_addr;
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|
|
|
for(i=0; i<rxbd_num; i=i+1) begin
|
|
buf_addr = `RX_BUF_BASE + i * 32'h600;
|
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bd_status_addr = `RX_BD_BASE + i * 8;
|
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bd_ptr_addr = bd_status_addr + 4;
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|
|
|
// Initializing BD - status
|
|
if(i==rxbd_num-1)
|
|
WishboneWrite(32'h0000e000, bd_status_addr); // last BD: + WRAP
|
|
else
|
|
WishboneWrite(32'h0000c000, bd_status_addr); // IRQ + PAD + CRC
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|
|
WishboneWrite(buf_addr, bd_ptr_addr); // Initializing BD - pointer
|
|
end
|
|
endtask // initialize_rxbd
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|
|
reg [7:0] LateCollisionCounter;
|
reg [7:0] LateCollisionCounter;
|
reg EnableCollisionCounter;
|
reg EnableCollisionCounter;
|
// Making a late collision
|
// Making a late collision
|
|
|
initial
|
initial
|
Line 1085... |
Line 969... |
|
|
always @ (posedge WB_CLK_I)
|
always @ (posedge WB_CLK_I)
|
begin
|
begin
|
if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
|
if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
|
begin
|
begin
|
repeat(3) @ (posedge WB_CLK_I);
|
repeat(2) @ (posedge WB_CLK_I);
|
begin
|
begin
|
m_wb_ack_i <=#Tp 1'b1;
|
m_wb_ack_i <=#Tp 1'b1;
|
if(~m_wb_we_o)
|
if(~m_wb_we_o)
|
begin
|
begin
|
#Tp;
|
#Tp;
|
Line 1385... |
Line 1269... |
WishboneWrite(TempData, TempAddr); // Writing status to TxBD
|
WishboneWrite(TempData, TempAddr); // Writing status to TxBD
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
task send_packet;
|
|
input [47:0] dest_addr;
|
|
input [15:0] length;
|
|
|
|
reg [31:0] BD, ptr;
|
|
reg [31:0] i;
|
|
reg [2:0] increment;
|
|
|
|
reg [31:0] TempAddr;
|
|
reg [31:0] TempData;
|
|
reg [15:0] kk;
|
|
reg [3:0] Select;
|
|
|
|
begin
|
|
bd_status_addr = `TX_BD_BASE + g_last_txbd * 8;
|
|
|
|
mama
|
|
WishboneRead(bd_status_addr, BD); // Read BD
|
|
WishboneRead(bd_status_addr+4, ptr); // Read buffer pointer
|
|
|
|
case(ptr[1:0])
|
|
2'h0 : begin Select = 4'hf; increment = 3'h4 end
|
|
2'h1 : begin Select = 4'h7; increment = 3'h3 end
|
|
2'h2 : begin Select = 4'h3; increment = 3'h2 end
|
|
2'h3 : begin Select = 4'h1; increment = 3'h1 end
|
|
endcase
|
|
|
|
// Writing data to buffer
|
|
for(i=ptr; i<(length+ptr); i=i+increment) // (i=0; i<length; i=i+increment)
|
|
begin
|
|
if(i>ptr) // After first write all accesses are word accesses
|
|
begin Select = 4'hf; increment=3'h4; end
|
|
|
|
TempAddr = `TX_BUF_BASE + TxBDIndex * 32'h600 + kk;
|
|
TempData = {i[7:0]+3'h1, i[7:0]+3'h2, i[7:0]+3'h3, i[7:0]+3'h4};
|
|
mama
|
|
WishboneWriteData(TempAddr, TempData, Select); // Writing Data to buffer that is pointed by the BD
|
|
end
|
|
|
|
|
|
// Writing buffer pointer
|
|
TempAddr = {22'h01, ((TxBDIndex*2'h2 + 1'b1)<<2)};
|
|
TempData = `TX_BUF_BASE + TxBDIndex * 32'h600 + AddrOffset; // 1536 bytes is reserved for one frame
|
|
WishboneWrite(TempData, TempAddr); // Writing Tx pointer
|
|
|
|
TempAddr = {22'h01, ((TxBDIndex*2'h2)<<2)};
|
|
TempData = {length[15:0], 1'b1, 1'b1, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready, interrupt and Wrap = 1
|
|
|
|
#1;
|
|
if(Wrap)
|
|
TxBDIndex = 0;
|
|
else
|
|
TxBDIndex = TxBDIndex + 1;
|
|
|
|
WishboneWrite(TempData, TempAddr); // Writing status to TxBD
|
|
|
|
if(BD & 32'h2000) // Wrap bit set ?
|
|
g_last_txbd = 0;
|
|
else
|
|
g_last_txbd = g_last_txbd+1;
|
|
|
|
end
|
|
endtask // send_packet
|
|
|
|
|
task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
input [15:0] LengthRx;
|
input [15:0] LengthRx;
|
input RxControlFrame;
|
input RxControlFrame;
|
input [31:0] TransferType; //Broadcast,Unicast,Multicast
|
input [31:0] TransferType; //Broadcast,Unicast,Multicast
|
Line 1585... |
Line 1533... |
LogEnable = 1'b1;
|
LogEnable = 1'b1;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
`endif
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|