Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.23 2002/11/22 02:12:16 mohor
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// test_mac_full_duplex_flow_control tests pretty much finished.
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// TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
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// FRM. AT 4 TX BD ( 10Mbps ) finished.
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// TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
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// TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
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//
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// Revision 1.22 2002/11/21 13:56:50 mohor
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// Revision 1.22 2002/11/21 13:56:50 mohor
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// test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
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// test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
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// finished.
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// finished.
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//
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//
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// Revision 1.21 2002/11/19 20:27:45 mohor
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// Revision 1.21 2002/11/19 20:27:45 mohor
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Line 449... |
Line 456... |
// test_mii(0, 17); // 0 - 17
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// test_mii(0, 17); // 0 - 17
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test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
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test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
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eth_phy.carrier_sense_real_delay(0);
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eth_phy.carrier_sense_real_delay(0);
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// test_mac_full_duplex_transmit(8, 9); // 0 - (21)
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// test_mac_full_duplex_transmit(8, 9); // 0 - (21)
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// test_mac_full_duplex_receive(8, 9);
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// test_mac_full_duplex_receive(8, 9);
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test_mac_full_duplex_flow_control(0, 2);
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test_mac_full_duplex_flow_control(2, 2);
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test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
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test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
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eth_phy.carrier_sense_real_delay(1);
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eth_phy.carrier_sense_real_delay(1);
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Line 14159... |
Line 14166... |
reg [ 7:0] st_data;
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reg [ 7:0] st_data;
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reg [15:0] max_tmp;
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reg [15:0] max_tmp;
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reg [15:0] min_tmp;
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reg [15:0] min_tmp;
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reg PassAll;
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reg PassAll;
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reg RxFlow;
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reg RxFlow;
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reg enable_irq_in_rxbd;
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begin
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begin
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// MAC FULL DUPLEX FLOW CONTROL TEST
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// MAC FULL DUPLEX FLOW CONTROL TEST
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test_heading("MAC FULL DUPLEX FLOW CONTROL TEST");
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test_heading("MAC FULL DUPLEX FLOW CONTROL TEST");
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$display(" ");
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$display(" ");
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$display("MAC FULL DUPLEX FLOW CONTROL TEST");
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$display("MAC FULL DUPLEX FLOW CONTROL TEST");
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Line 14699... |
Line 14707... |
// write to phy's control register for 10Mbps
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// write to phy's control register for 10Mbps
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#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
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#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
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#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
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#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
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speed = 10;
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speed = 10;
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// RXB and RXC interrupts masked
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wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
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`ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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// Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
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for (i=0; i<3; i=i+1)
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begin
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// choose generating carrier sense and collision for first and last 64 lengths of frames
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case (i)
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0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
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begin
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PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
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// enable interrupt generation
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set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
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// Set PASSALL = 0 and RXFLOW = 0
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wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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end
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1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
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begin
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PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
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// enable interrupt generation
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set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
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// Set PASSALL = 0 and RXFLOW = 0
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wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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end
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2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
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begin
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PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
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// enable interrupt generation
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set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
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// Set PASSALL = 0 and RXFLOW = 0
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wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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end
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default:
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begin
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$display("*E We should never get here !!!");
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test_fail("We should never get here !!!");
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fail = fail + 1;
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end
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endcase
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// not detect carrier sense in FD and no collision
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eth_phy.no_carrier_sense_rx_fd_detect(0);
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eth_phy.collision(0);
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// set wrap bit and empty bit
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set_rx_bd_wrap(127);
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set_rx_bd_empty(127, 127);
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fork
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begin
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#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
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repeat(10) @(posedge mrx_clk);
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end
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begin
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#1 check_rx_bd(127, data);
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wait (MRxDV === 1'b1); // start transmit
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#1 check_rx_bd(127, data);
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if (data[15] !== 1)
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begin
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$display("*E Wrong buffer descriptor's ready bit read out from MAC");
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test_fail("Wrong buffer descriptor's ready bit read out from MAC");
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fail = fail + 1;
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end
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wait (MRxDV === 1'b0); // end transmit
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repeat(50) @(posedge mrx_clk); // Wait some time so frame is received and
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repeat (100) @(posedge wb_clk); // status/irq is written.
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end
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join
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#1 check_rx_bd(127, data);
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// Checking buffer descriptor
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if(PassAll)
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begin
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if(enable_irq_in_rxbd)
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begin
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if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
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begin
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$display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
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$display("RxBD = 0x%0x", data);
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test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
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fail = fail + 1;
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end
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end
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else
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begin
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if(data !== 32'h402100) // Rx BD must not be marked as EMPTY (control frame is received)
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begin
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$display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
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$display("RxBD = 0x%0x", data);
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test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
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fail = fail + 1;
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end
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end
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end
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else
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begin
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if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
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begin
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$display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
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$display("RxBD = 0x%0x", data);
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test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
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fail = fail + 1;
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end
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end
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// Checking if interrupt was generated
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if (wb_int)
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begin
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`TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
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test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
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fail = fail + 1;
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end
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wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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if(RxFlow)
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begin
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if(data !== (`ETH_INT_RXC))
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begin
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test_fail("RXC is not set or multiple IRQs active!");
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fail = fail + 1;
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`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
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end
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// Clear RXC interrupt
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wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
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end
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else if(enable_irq_in_rxbd)
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begin
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if(data !== (`ETH_INT_RXB))
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begin
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test_fail("RXB is not set or multiple IRQs active!");
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fail = fail + 1;
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`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
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end
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// Clear RXC interrupt
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wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
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end
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else
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begin
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if(data !== 0)
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begin
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test_fail("Some IRQs is active!");
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fail = fail + 1;
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`TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
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end
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end
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end
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// End: Test is irq is set while RXB and RXC interrupts are masked.
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// Now all interrupts are unmasked. Performing tests again.
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wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
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wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
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`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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for (i=0; i<4; i=i+1)
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for (i=0; i<4; i=i+1)
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// i=3;
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begin
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begin
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$display("i=%0d", i);
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// choose generating carrier sense and collision for first and last 64 lengths of frames
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// choose generating carrier sense and collision for first and last 64 lengths of frames
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case (i)
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case (i)
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0: // PASSALL = 0, RXFLOW = 0
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0: // PASSALL = 0, RXFLOW = 0
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begin
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begin
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PassAll=0; RxFlow=0;
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PassAll=0; RxFlow=0;
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