Line 1... |
Line 1... |
///////////3///////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// tb_eth_top.v ////
|
//// tb_eth_top.v ////
|
//// ////
|
//// ////
|
//// This file is part of the Ethernet IP core project ////
|
//// This file is part of the Ethernet IP core project ////
|
//// http://www.opencores.org/projects/ethmac/ ////
|
//// http://www.opencores.org/projects/ethmac/ ////
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Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.9 2002/02/14 20:14:38 billditt
|
|
// Added separate tests for Multicast, Unicast, Broadcast
|
|
//
|
|
// Revision 1.8 2002/02/12 20:24:00 mohor
|
|
// HASH0 and HASH1 register read/write added.
|
|
//
|
// Revision 1.7 2002/02/06 14:11:35 mohor
|
// Revision 1.7 2002/02/06 14:11:35 mohor
|
// non-DMA host interface added. Select the right configutation in eth_defines.
|
// non-DMA host interface added. Select the right configutation in eth_defines.
|
//
|
//
|
// Revision 1.6 2001/12/08 12:36:00 mohor
|
// Revision 1.6 2001/12/08 12:36:00 mohor
|
// TX_BD_NUM register added instead of the RB_BD_ADDR.
|
// TX_BD_NUM register added instead of the RB_BD_ADDR.
|
Line 133... |
Line 139... |
reg [3:0] MRxD;
|
reg [3:0] MRxD;
|
reg MRxDV;
|
reg MRxDV;
|
reg MRxErr;
|
reg MRxErr;
|
reg MColl;
|
reg MColl;
|
reg MCrs;
|
reg MCrs;
|
reg RxAbort;
|
|
|
|
reg Mdi_I;
|
reg Mdi_I;
|
wire Mdo_O;
|
wire Mdo_O;
|
wire Mdo_OE;
|
wire Mdo_OE;
|
wire Mdc_O;
|
wire Mdc_O;
|
|
|
|
|
|
|
reg GSR;
|
|
|
|
reg WishboneBusy;
|
reg WishboneBusy;
|
reg StartTB;
|
reg StartTB;
|
reg [9:0] TxBDIndex;
|
reg [9:0] TxBDIndex;
|
reg [9:0] RxBDIndex;
|
reg [9:0] RxBDIndex;
|
|
|
Line 181... |
Line 184... |
.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
|
.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
|
|
|
//RX
|
//RX
|
.mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
|
.mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
|
.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
|
.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
|
.RxAbort(RxAbort), // igor !!! Ta se mora preseliti da bo prisel iz enega izmed modulov. Tu je le zaradi
|
|
// testiranja. Pove, kdaj adresa ni ustrezala in se paketi sklirajo, stevci pa resetirajo.
|
|
|
|
// MIIM
|
// MIIM
|
.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
|
.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
|
|
|
.int_o()
|
.int_o()
|
Line 219... |
Line 220... |
MRxD = 4'h0;
|
MRxD = 4'h0;
|
MRxDV = 1'b0;
|
MRxDV = 1'b0;
|
MRxErr = 1'b0;
|
MRxErr = 1'b0;
|
MColl = 1'b0;
|
MColl = 1'b0;
|
MCrs = 1'b0;
|
MCrs = 1'b0;
|
RxAbort = 1'b0;
|
|
Mdi_I = 1'b0;
|
Mdi_I = 1'b0;
|
|
|
WishboneBusy = 1'b0;
|
WishboneBusy = 1'b0;
|
TxBDIndex = 10'h0;
|
TxBDIndex = 10'h0;
|
RxBDIndex = 10'h0;
|
RxBDIndex = 10'h0;
|
Line 237... |
Line 237... |
`else
|
`else
|
mcd1 = $fopen("ethernet_tx.log");
|
mcd1 = $fopen("ethernet_tx.log");
|
mcd2 = $fopen("ethernet_rx.log");
|
mcd2 = $fopen("ethernet_rx.log");
|
`endif
|
`endif
|
WB_RST_I = 1'b1;
|
WB_RST_I = 1'b1;
|
GSR = 1'b1;
|
|
#100 WB_RST_I = 1'b0;
|
#100 WB_RST_I = 1'b0;
|
GSR = 1'b0;
|
|
#100 StartTB = 1'b1;
|
#100 StartTB = 1'b1;
|
end
|
end
|
|
|
|
|
//assign glbl.GSR = GSR;
|
|
|
|
|
|
|
|
// Generating WB_CLK_I clock
|
// Generating WB_CLK_I clock
|
always
|
always
|
begin
|
begin
|
// forever #2.5 WB_CLK_I = ~WB_CLK_I; // 2*2.5 ns -> 200.0 MHz
|
// forever #2.5 WB_CLK_I = ~WB_CLK_I; // 2*2.5 ns -> 200.0 MHz
|
Line 285... |
Line 280... |
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
|
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
|
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
|
WishboneWrite(32'h0040000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
|
|
|
|
|
|
|
|
SendPacket(16'h0015, 1'b0);
|
SendPacket(16'h0015, 1'b0);
|
SendPacket(16'h0043, 1'b1); // Control frame
|
SendPacket(16'h0043, 1'b1); // Control frame
|
SendPacket(16'h0025, 1'b0);
|
SendPacket(16'h0025, 1'b0);
|
SendPacket(16'h0045, 1'b0);
|
SendPacket(16'h0045, 1'b0);
|
SendPacket(16'h0025, 1'b0);
|
SendPacket(16'h0025, 1'b0);
|
|
|
|
|
ReceivePacket(16'h0012, 1'b1); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
|
ReceivePacket(16'h0012, 1'b1); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
|
ReceivePacket(16'h0011, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0011, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
Line 343... |
Line 334... |
WB_WE_I = 1'b1;
|
WB_WE_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_SEL_I = 4'hf;
|
WB_SEL_I = 4'hf;
|
|
|
// for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
|
|
// begin
|
|
// @ (posedge WB_CLK_I);
|
|
// end
|
|
|
|
// if(ii==20)
|
|
// begin
|
|
// $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
|
|
// Data, Address, $time);
|
|
// #50 $stop;
|
|
// end
|
|
|
|
wait(WB_ACK_O); // waiting for acknowledge response
|
wait(WB_ACK_O); // waiting for acknowledge response
|
|
|
// Writing information about the access to the screen
|
// Writing information about the access to the screen
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
if(~Address[11] & ~Address[10])
|
if(~Address[11] & ~Address[10])
|
Line 543... |
Line 522... |
|
|
wait (~WishboneBusy);
|
wait (~WishboneBusy);
|
WishboneBusy = 1;
|
WishboneBusy = 1;
|
#1;
|
#1;
|
WB_DAT_I = {a, b, c, d};
|
WB_DAT_I = {a, b, c, d};
|
// WB_ADR_I = {20'h20, pp[11:0]};
|
|
WB_ADR_I = {22'h02, pp[9:0]};
|
WB_ADR_I = {22'h02, pp[9:0]};
|
$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
|
$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
|
|
|
WB_WE_I = 1'b1;
|
WB_WE_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
Line 580... |
Line 558... |
repeat(Delay) @(posedge WB_CLK_I);
|
repeat(Delay) @(posedge WB_CLK_I);
|
|
|
wait (~WishboneBusy);
|
wait (~WishboneBusy);
|
WishboneBusy = 1;
|
WishboneBusy = 1;
|
#1;
|
#1;
|
// WB_ADR_I = {20'h20, rr[11:0]};
|
|
WB_ADR_I = {22'h02, rr[9:0]};
|
WB_ADR_I = {22'h02, rr[9:0]};
|
$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
|
$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
|
|
|
WB_WE_I = 1'b1;
|
WB_WE_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
Line 699... |
Line 676... |
`else // No WISHBONE_DMA
|
`else // No WISHBONE_DMA
|
|
|
initial
|
initial
|
begin
|
begin
|
wait(StartTB); // Start of testbench
|
wait(StartTB); // Start of testbench
|
//IGORS_BOILER_PLATE;
|
|
|
InitializeMemory;
|
|
|
|
// Select which test you want to run:
|
|
TestTxAndRx;
|
// TestUnicast;
|
// TestUnicast;
|
// TestBroadcast;
|
// TestBroadcast;
|
TestMulticast;
|
// TestMulticast;
|
end
|
end
|
|
|
task IGORS_BOILER_PLATE;
|
task TestTxAndRx;
|
begin
|
begin
|
$display("\nBegin IGORS_BOILER_PLATE \n");
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
|
|
|
|
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
|
|
|
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
|
|
|
|
|
WishboneWrite(32'h00002463, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, CrcEn, Pad off, full duplex, r_IFG, promisc ON
|
|
|
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
|
|
|
SendPacket(16'h0010, 1'b0);
|
SendPacket(16'h0007, 1'b0);
|
SendPacket(16'h0011, 1'b0);
|
SendPacket(16'h0011, 1'b0);
|
SendPacket(16'h0012, 1'b0);
|
SendPacket(16'h0012, 1'b0);
|
SendPacket(16'h0013, 1'b0);
|
SendPacket(16'h0013, 1'b0);
|
SendPacket(16'h0014, 1'b0);
|
SendPacket(16'h0014, 1'b0);
|
|
|
Line 733... |
Line 711... |
SendPacket(16'h0025, 1'b0);
|
SendPacket(16'h0025, 1'b0);
|
SendPacket(16'h0045, 1'b0);
|
SendPacket(16'h0045, 1'b0);
|
SendPacket(16'h0025, 1'b0);
|
SendPacket(16'h0025, 1'b0);
|
SendPacket(16'h0017, 1'b0);
|
SendPacket(16'h0017, 1'b0);
|
|
|
// ReceivePacket(16'h0012, 1'b1, 1'b0);
|
ReceivePacket(16'h0015, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
|
ReceivePacket(16'h0016, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacket(16'h0017, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacket(16'h0018, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
|
WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
|
|
WishboneRead({26'h0, `ETH_HASH1_ADR}); // read back
|
|
|
|
$display("\n Set Hash Filter to accept this Multicast packet, send packets\n");
|
|
|
|
ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacket(16'h0016, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacket(16'h0017, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacket(16'h0018, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
|
|
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
|
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
|
|
|
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
|
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
|
|
|
Line 769... |
Line 737... |
WishboneRead({22'h01, (10'h85<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h85<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
|
|
|
#100000 $stop;
|
#100000 $stop;
|
$display("\nEnd IGORS_BOILER_PLATE \n");
|
|
end
|
end
|
endtask //IGORS_BOILER_PLATE
|
endtask //TestTxAndRx
|
|
|
|
|
task TestUnicast;
|
task TestUnicast;
|
begin
|
begin
|
$display("\nBegin TestUnicast \n");
|
$display("\nBegin TestUnicast \n");
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
|
|
WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, CrcEn, no Pad, r_IFG, promisc off, broadcast on
|
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
|
|
|
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
|
|
|
|
|
|
|
SendPacket(16'h0010, 1'b0);
|
|
SendPacket(16'h0011, 1'b0);
|
|
SendPacket(16'h0012, 1'b0);
|
|
SendPacket(16'h0013, 1'b0);
|
|
SendPacket(16'h0014, 1'b0);
|
|
|
|
SendPacket(16'h0030, 1'b0);
|
|
SendPacket(16'h0031, 1'b0);
|
|
SendPacket(16'h0032, 1'b0);
|
|
SendPacket(16'h0033, 1'b0);
|
|
SendPacket(16'h0025, 1'b0);
|
|
SendPacket(16'h0045, 1'b0);
|
|
SendPacket(16'h0025, 1'b0);
|
|
SendPacket(16'h0017, 1'b0);
|
|
|
|
// ReceivePacket(16'h0012, 1'b1, 1'b0); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
|
|
$display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
|
$display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
|
|
|
ReceivePacket(16'h0015, 1'b0, 1'b0,`UNICAST_XFR);
|
ReceivePacket(16'h0014, 1'b0,`UNICAST_XFR);
|
|
|
WishboneWrite(32'h04030200, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address
|
WishboneWrite(32'h04030200, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address
|
WishboneWrite(32'h00000605, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
|
WishboneWrite(32'h00000605, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
|
|
|
|
|
$display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
|
$display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
|
|
|
ReceivePacket(16'h0015, 1'b0, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0015, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0016, 1'b0, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0016, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0017, 1'b0, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0017, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0018, 1'b0, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0018, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
|
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
|
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
|
|
|
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
|
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
|
|
|
WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register
|
|
|
|
|
|
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h85<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h85<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
|
|
WishboneRead({22'h01, (10'h88<<2)}); // Read from RxBD register
|
|
WishboneRead({22'h01, (10'h89<<2)}); // Read from RxBD register
|
|
|
#100000 $stop;
|
#100000 $stop;
|
$display("\nEnd TestUnicast \n");
|
$display("\nEnd TestUnicast \n");
|
end
|
end
|
endtask //TestUnicast
|
endtask //TestUnicast
|
Line 848... |
Line 790... |
begin
|
begin
|
$display("\nBegin TestMulticast \n");
|
$display("\nBegin TestMulticast \n");
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
|
|
WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, CrcEn, No Pad, r_IFG, promiscuos off, broadcast enable
|
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
|
|
|
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
|
|
|
|
|
|
|
SendPacket(16'h0010, 1'b0);
|
|
SendPacket(16'h0011, 1'b0);
|
|
SendPacket(16'h0012, 1'b0);
|
|
SendPacket(16'h0013, 1'b0);
|
|
SendPacket(16'h0014, 1'b0);
|
|
|
|
SendPacket(16'h0030, 1'b0);
|
|
SendPacket(16'h0031, 1'b0);
|
|
SendPacket(16'h0032, 1'b0);
|
|
SendPacket(16'h0033, 1'b0);
|
|
SendPacket(16'h0025, 1'b0);
|
|
SendPacket(16'h0045, 1'b0);
|
|
SendPacket(16'h0025, 1'b0);
|
|
SendPacket(16'h0017, 1'b0);
|
|
|
|
// ReceivePacket(16'h0012, 1'b1, 1'b0);
|
|
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
|
|
|
|
$display("\n This Multicast packet will be rejected by Hash Filter\n");
|
$display("\n This Multicast packet will be rejected by Hash Filter\n");
|
|
|
ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR);
|
ReceivePacket(16'h0014, 1'b0,`MULTICAST_XFR);
|
|
|
WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
|
WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
|
WishboneRead({26'h0, `ETH_HASH1_ADR}); // read back
|
WishboneRead({26'h0, `ETH_HASH1_ADR, 2'h0}); // read back
|
|
|
$display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
|
$display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
|
|
|
ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0015, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0016, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0016, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0017, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0017, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0018, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
ReceivePacket(16'h0018, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
|
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
|
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
|
|
|
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
|
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
|
|
|
WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register
|
|
|
|
|
|
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h85<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h85<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
|
|
|
#100000 $stop;
|
|
$display("\nEnd TestMulticast \n");
|
$display("\nEnd TestMulticast \n");
|
|
#100000 $stop;
|
end
|
end
|
endtask //TestMulticast
|
endtask //TestMulticast
|
|
|
|
|
task TestBroadcast;
|
task TestBroadcast;
|
begin
|
begin
|
$display("\nBegin TestBroadcast \n");
|
$display("\n\n\nBegin TestBroadcast");
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
|
|
|
WishboneWrite(32'h0002A44b, {26'h0, `ETH_MODER_ADR, 2'h0});
|
WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
|
// RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG, r_Bro = 1 (disabled)
|
|
|
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
|
|
|
|
$display("\nThis Broadcast packet will be rejected, r_BRO = 1");
|
|
ReceivePacket(16'h0014, 1'b0,`BROADCAST_XFR);
|
|
|
|
$display("\nSet r_Bro = 0, resend packet");
|
SendPacket(16'h0010, 1'b0);
|
WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
|
SendPacket(16'h0011, 1'b0);
|
ReceivePacket(16'h0015, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
SendPacket(16'h0012, 1'b0);
|
|
SendPacket(16'h0013, 1'b0);
|
$display("\n This Broadcast packet will be rejected, r_BRO = 1");
|
SendPacket(16'h0014, 1'b0);
|
WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
|
|
ReceivePacket(16'h0016, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
SendPacket(16'h0030, 1'b0);
|
ReceivePacket(16'h0017, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
SendPacket(16'h0031, 1'b0);
|
|
SendPacket(16'h0032, 1'b0);
|
$display("\n Set r_Bro = 0, resend packet");
|
SendPacket(16'h0033, 1'b0);
|
WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
|
SendPacket(16'h0025, 1'b0);
|
ReceivePacket(16'h0018, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
SendPacket(16'h0045, 1'b0);
|
|
SendPacket(16'h0025, 1'b0);
|
|
SendPacket(16'h0017, 1'b0);
|
|
|
|
// ReceivePacket(16'h0012, 1'b1, 1'b0);
|
|
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
|
|
|
|
$display("\n This Broadcast packet will be rejected ,r_BRO set\n");
|
|
|
|
ReceivePacket(16'h0015, 1'b0, 1'b0,`BROADCAST_XFR);
|
|
|
|
|
|
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});
|
|
|
|
// RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG, r_Bro
|
|
$display("\n Set r_Bro, resend packet\n");
|
|
|
|
ReceivePacket(16'h0015, 1'b0, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacket(16'h0016, 1'b0, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacket(16'h0017, 1'b0, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
ReceivePacket(16'h0018, 1'b0, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
|
|
|
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
|
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
|
|
|
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
|
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
|
|
|
WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register
|
|
WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register
|
|
|
|
|
|
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register
|
WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register
|
Line 985... |
Line 870... |
#100000 $stop;
|
#100000 $stop;
|
$display("\nEnd TestBroadcast \n");
|
$display("\nEnd TestBroadcast \n");
|
end
|
end
|
endtask //TestBroadcast
|
endtask //TestBroadcast
|
|
|
//integer ijk;
|
|
|
|
//initial
|
|
//ijk = 0; // for stoping generation of the m_wb_ack_i signal at the right moment so we get underrun
|
|
|
|
// Answering to master Wishbone requests
|
|
always @ (posedge WB_CLK_I)
|
always @ (posedge WB_CLK_I)
|
begin
|
begin
|
if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
|
if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
|
begin
|
begin
|
repeat(3) @ (posedge WB_CLK_I);
|
repeat(3) @ (posedge WB_CLK_I);
|
begin
|
begin
|
// if(ijk==41)
|
|
// begin
|
|
// repeat(1000) @ (posedge WB_CLK_I);
|
|
// end
|
|
// else
|
|
m_wb_ack_i <=#Tp 1'b1;
|
m_wb_ack_i <=#Tp 1'b1;
|
if(~m_wb_we_o)
|
if(~m_wb_we_o)
|
begin
|
begin
|
#Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
|
#Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
|
$fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
|
$fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
|
// ijk = ijk + 1;
|
|
end
|
end
|
else
|
else
|
$fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
|
$fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
|
end
|
end
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
Line 1057... |
Line 931... |
else
|
else
|
if(~Address[11] & Address[10])
|
if(~Address[11] & Address[10])
|
if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
|
if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
|
begin
|
begin
|
$write("\n(%0t) Write to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, Data, Address);
|
$write("\n(%0t) Write to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, Data, Address);
|
if(Data[9])
|
if(Address[9:2] == tb_eth_top.ethtop.r_TxBDNum-2'h2)
|
$write("(%0t) Send Control packet (PAUSE = 0x%0h)\n", $time, Data[31:16]);
|
$write("(%0t) Send Control packet\n", $time);
|
end
|
end
|
else
|
else
|
$write("\n(%0t) Write to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, Data, Address);
|
$write("\n(%0t) Write to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, Data, Address);
|
else
|
else
|
$write("\n(%0t) WB write ?????????????? Data: 0x%x Addr: 0x%0x", $time, Data, Address);
|
$write("\n(%0t) WB write ?????????????? Data: 0x%x Addr: 0x%0x", $time, Data, Address);
|
Line 1137... |
Line 1011... |
TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
|
TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
|
TempData = 32'h78563411;
|
TempData = 32'h78563411;
|
WishboneWrite(TempData, TempAddr); // buffer pointer
|
WishboneWrite(TempData, TempAddr); // buffer pointer
|
|
|
|
|
TempAddr = {22'h01, (TxBDIndex<<2)}; // igor !!! zbrisi spodnjo vrstico
|
TempAddr = {22'h01, (TxBDIndex<<2)};
|
// TempAddr = {22'h01, 10'b1010010100};
|
|
|
|
TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
|
TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
|
|
|
#1;
|
#1;
|
// if(TxBDIndex == 6) // Only 4 buffer descriptors are used
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// if(TxBDIndex == 6) // Only 4 buffer descriptors are used
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Line 1157... |
Line 1030... |
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task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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input [15:0] LengthRx;
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input [15:0] LengthRx;
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input RxControlFrame;
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input RxControlFrame;
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input Abort;
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input [31:0] TransferType; //Broadcast,Unicast,Multicast
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input [31:0] TransferType; //Broadcast,Unicast,Multicast
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reg WrapRx;
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reg WrapRx;
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reg [31:0] TempRxAddr;
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reg [31:0] TempRxAddr;
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reg [31:0] TempRxData;
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reg [31:0] TempRxData;
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reg abc;
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reg abc;
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Line 1193... |
Line 1065... |
begin
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begin
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#200;
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#200;
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if(RxControlFrame)
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if(RxControlFrame)
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GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
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GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
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else
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else
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GetDataOnMRxD(LengthRx, Abort, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
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GetDataOnMRxD(LengthRx, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
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end
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end
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end
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end
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endtask
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endtask
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task GetDataOnMRxD;
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task GetDataOnMRxD;
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input [15:0] Len;
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input [15:0] Len;
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input abort;
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input [31:0] TransferType;
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input [31:0] TransferType;
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integer tt;
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integer tt;
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begin
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begin
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@ (posedge MRxClk);
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@ (posedge MRxClk);
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Line 1229... |
Line 1100... |
else if(TransferType == `BROADCAST_XFR && tt < 7)
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else if(TransferType == `BROADCAST_XFR && tt < 7)
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MRxD = 4'hf;
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MRxD = 4'hf;
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else
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else
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MRxD=tt[3:0]; // Multicast transfer
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MRxD=tt[3:0]; // Multicast transfer
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if(tt==9)
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RxAbort<=#1 abort;
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@ (posedge MRxClk);
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@ (posedge MRxClk);
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|
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if(TransferType == `BROADCAST_XFR && tt < 7)
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if(TransferType == `BROADCAST_XFR && tt < 7)
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MRxD = 4'hf;
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MRxD = 4'hf;
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else
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else
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MRxD=tt[7:4];
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MRxD=tt[7:4];
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RxAbort<=#1 0;
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end
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end
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@ (posedge MRxClk);
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@ (posedge MRxClk);
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MRxDV=1'b0;
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MRxDV=1'b0;
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end
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end
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Line 1254... |
Line 1122... |
reg [127:0] Data;
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reg [127:0] Data;
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reg [31:0] Crc;
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reg [31:0] Crc;
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integer tt;
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integer tt;
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|
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begin
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begin
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//Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
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Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
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|
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Crc = 32'h6014fe08; // not a correct value
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Crc = 32'h6014fe08; // not a correct value
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|
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@ (posedge MRxClk);
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@ (posedge MRxClk);
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MRxDV=1'b1;
|
MRxDV=1'b1;
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Line 1308... |
Line 1175... |
|
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@ (posedge MRxClk);
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@ (posedge MRxClk);
|
MRxDV=1'b0;
|
MRxDV=1'b0;
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end
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end
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endtask
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endtask
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|
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task InitializeMemory;
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reg [9:0] mem_addr;
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|
|
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begin
|
|
for(mem_addr=0; mem_addr<=10'h0ff; mem_addr=mem_addr+1'b1)
|
|
WishboneWrite(32'h0, {22'h01, mem_addr<<2}); // Writing status to RxBD
|
|
end
|
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endtask
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|
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`endif
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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