Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.5 2001/10/19 11:24:04 mohor
|
|
// Number of addresses (wb_adr_i) minimized.
|
|
//
|
// Revision 1.4 2001/10/19 08:46:53 mohor
|
// Revision 1.4 2001/10/19 08:46:53 mohor
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// simulation of the few cores in a one joined project.
|
// simulation of the few cores in a one joined project.
|
//
|
//
|
// Revision 1.3 2001/09/24 14:55:49 mohor
|
// Revision 1.3 2001/09/24 14:55:49 mohor
|
Line 232... |
Line 235... |
begin
|
begin
|
wait(StartTB); // Start of testbench
|
wait(StartTB); // Start of testbench
|
|
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
|
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
|
WishboneWrite(32'h00000080, {26'h0, `ETH_RX_BD_ADR_ADR<<2}); // r_RxBDAddress = 0x80
|
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
|
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
|
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
|
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
|
|
|
|
|
|
|
Line 313... |
Line 316... |
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
if(~Address[11] & ~Address[10])
|
if(~Address[11] & ~Address[10])
|
$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
|
$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
|
else
|
else
|
if(~Address[11] & Address[10])
|
if(~Address[11] & Address[10])
|
if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
|
if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
|
begin
|
begin
|
$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
|
$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
|
if(Data[9])
|
if(Data[9])
|
$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
|
$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
|
end
|
end
|
Line 369... |
Line 372... |
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
if(~Address[11] & ~Address[10])
|
if(~Address[11] & ~Address[10])
|
$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
|
$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
|
else
|
else
|
if(~Address[11] & Address[10])
|
if(~Address[11] & Address[10])
|
if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
|
if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
|
begin
|
begin
|
$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
|
$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
|
end
|
end
|
else
|
else
|
$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
|
$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
|
Line 440... |
Line 443... |
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
WrapRx = 1'b1;
|
WrapRx = 1'b1;
|
else
|
else
|
WrapRx = 1'b0;
|
WrapRx = 1'b0;
|
|
|
TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
|
TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
|
|
|
TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
|
TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
|
|
|
#1;
|
#1;
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|