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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 264 and 269
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Rev 264 |
Rev 269 |
Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.47 2002/11/22 13:26:21 mohor
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// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
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// anywhere. Removed.
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//
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// Revision 1.46 2002/11/22 01:57:06 mohor
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// Revision 1.46 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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// synchronized.
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//
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//
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// Revision 1.45 2002/11/19 17:33:34 mohor
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// Revision 1.45 2002/11/19 17:33:34 mohor
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Line 941... |
Line 945... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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else
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else
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if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
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if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket | TxRetryPacket)))
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BlockReadTxDataFromMemory <=#Tp 1'b1;
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BlockReadTxDataFromMemory <=#Tp 1'b1;
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else
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else
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if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
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if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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end
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end
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