Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.30 2002/07/23 15:28:31 mohor
|
|
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
|
|
//
|
// Revision 1.29 2002/07/20 00:41:32 mohor
|
// Revision 1.29 2002/07/20 00:41:32 mohor
|
// ShiftEnded synchronization changed.
|
// ShiftEnded synchronization changed.
|
//
|
//
|
// Revision 1.28 2002/07/18 16:11:46 mohor
|
// Revision 1.28 2002/07/18 16:11:46 mohor
|
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
|
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
|
Line 932... |
Line 935... |
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
end
|
end
|
|
6'b10_00_0_1, 6'b01_00_0_1 :
|
|
begin
|
|
MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
|
|
MasterWbRX <=#Tp 1'b0;
|
|
m_wb_cyc_o <=#Tp 1'b0;
|
|
m_wb_stb_o <=#Tp 1'b0;
|
|
end
|
default: // Don't touch
|
default: // Don't touch
|
begin
|
begin
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbRX <=#Tp MasterWbRX;
|
MasterWbRX <=#Tp MasterWbRX;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
Line 1847... |
Line 1857... |
.clear(RxFifoReset), .full(RxBufferFull),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.empty(RxBufferEmpty), .cnt()
|
.empty(RxBufferEmpty), .cnt()
|
);
|
);
|
|
|
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
|
assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;
|
|
|
|
|
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|