Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/09/18 16:40:40 mohor
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// Simple testbench that includes eth_cop, eth_host and eth_memory modules.
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// This testbench is used for testing the whole environment. Use tb_ethernet
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// testbench for testing just the ethernet MAC core (many tests).
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//
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//
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//
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//
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//
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//
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//
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Line 104... |
Line 109... |
// Ethernet Master Interface signals
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// Ethernet Master Interface signals
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wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
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wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
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wire [3:0] eth_ma_wb_sel_o;
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wire [3:0] eth_ma_wb_sel_o;
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wire eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
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wire eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
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`ifdef ETH_WISHBONE_B3
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wire [2:0] eth_ma_wb_cti_o;
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wire [1:0] eth_ma_wb_bte_o;
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`endif
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// Host Master Interface signals
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// Host Master Interface signals
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wire [31:0] host_ma_wb_adr_o, host_ma_wb_dat_i, host_ma_wb_dat_o;
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wire [31:0] host_ma_wb_adr_o, host_ma_wb_dat_i, host_ma_wb_dat_o;
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wire [3:0] host_ma_wb_sel_o;
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wire [3:0] host_ma_wb_sel_o;
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wire host_ma_wb_we_o, host_ma_wb_cyc_o, host_ma_wb_stb_o, host_ma_wb_ack_i, host_ma_wb_err_i;
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wire host_ma_wb_we_o, host_ma_wb_cyc_o, host_ma_wb_stb_o, host_ma_wb_ack_i, host_ma_wb_err_i;
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Line 156... |
Line 167... |
// WISHBONE master
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// WISHBONE master
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.m_wb_adr_o(eth_ma_wb_adr_o), .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
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.m_wb_adr_o(eth_ma_wb_adr_o), .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
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.m_wb_dat_i(eth_ma_wb_dat_i), .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
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.m_wb_dat_i(eth_ma_wb_dat_i), .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
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.m_wb_stb_o(eth_ma_wb_stb_o), .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
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.m_wb_stb_o(eth_ma_wb_stb_o), .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
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`ifdef ETH_WISHBONE_B3
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.m_wb_cti_o(eth_ma_wb_cti_o), .m_wb_bte_o(eth_ma_wb_bte_o),
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`endif
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//TX
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//TX
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.mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
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.mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
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//RX
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//RX
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.mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
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.mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
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Line 167... |
Line 182... |
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// MIIM
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// MIIM
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.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
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.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
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.int_o()
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.int_o()
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// Bist
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`ifdef ETH_BIST
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, .trst(1'b0), .SO(), .SI(1'b0), .shift_DR(1'b0), .capture_DR(1'b0), .extest(1'b0), .tck(1'b0)
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`endif
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);
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);
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// Connecting Memory Interface Module
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// Connecting Memory Interface Module
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Line 232... |
Line 253... |
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// Generating wb_clk_o clock
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// Generating wb_clk_o clock
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initial
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initial
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begin
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begin
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wb_clk_o=0;
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wb_clk_o=0;
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forever #20 wb_clk_o = ~wb_clk_o; // 2*20 ns -> 25 MHz
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// forever #20 wb_clk_o = ~wb_clk_o; // 2*20 ns -> 25 MHz
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forever #12.5 wb_clk_o = ~wb_clk_o; // 2*12.5 ns -> 40 MHz
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end
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end
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// Generating mtx_clk clock
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// Generating mtx_clk clock
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initial
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initial
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begin
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begin
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Line 261... |
Line 283... |
eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
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eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
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eth_host.wb_write(`ETH_MAC_ADDR1, 4'hf, 32'h0002); // Set ETH_MAC_ADDR1 register
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eth_host.wb_write(`ETH_MAC_ADDR1, 4'hf, 32'h0002); // Set ETH_MAC_ADDR1 register
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eth_host.wb_write(`ETH_MAC_ADDR0, 4'hf, 32'h03040506); // Set ETH_MAC_ADDR0 register
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eth_host.wb_write(`ETH_MAC_ADDR0, 4'hf, 32'h03040506); // Set ETH_MAC_ADDR0 register
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initialize_txbd(3);
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initialize_txbd(3);
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initialize_rxbd(2);
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initialize_rxbd(4);
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// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
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// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
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// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
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// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
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// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN |
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// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN |
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// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
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// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
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eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_BRO |
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// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_BRO |
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`ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
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// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
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// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
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// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
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// `ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK); // Set MODER register
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// `ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK); // Set MODER register
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// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
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eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
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// `ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK |
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`ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK |
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// `ETH_MODER_FULLD); // Set MODER register
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`ETH_MODER_FULLD); // Set MODER register
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eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
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eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
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set_packet(16'h64, 8'h1);
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set_packet(16'h364, 8'h1);
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set_packet(16'h34, 8'h11);
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set_packet(16'h234, 8'h11);
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send_packet;
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send_packet;
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set_packet(16'h34, 8'h21);
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repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
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set_packet(16'h34, 8'h31);
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// repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
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set_packet(16'h534, 8'h21);
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// set_packet(16'h34, 8'h31);
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/*
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/*
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eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h4); // Enable Tx Flow control
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eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h4); // Enable Tx Flow control
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eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h5); // Enable Tx Flow control
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eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h5); // Enable Tx Flow control
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eth_host.wb_write(`ETH_TX_CTRL, 4'hf, 32'h10013); // Send Control frame with PAUSE_TV=0x0013
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eth_host.wb_write(`ETH_TX_CTRL, 4'hf, 32'h10013); // Send Control frame with PAUSE_TV=0x0013
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*/
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*/
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send_packet;
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repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
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send_packet;
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send_packet;
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repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
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/*
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send_packet;
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*/
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GetDataOnMRxD(100, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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repeat (1000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
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repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
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GetDataOnMRxD(500, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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/*
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GetDataOnMRxD(113, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
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repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
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GetDataOnMRxD(500, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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GetDataOnMRxD(1200, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
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GetDataOnMRxD(1000, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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GetDataOnMRxD(1200, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
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GetDataOnMRxD(1000, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
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*/
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// Reading and printing interrupts
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// Reading and printing interrupts
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eth_host.wb_read(`ETH_INT, 4'hf, tmp);
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eth_host.wb_read(`ETH_INT, 4'hf, tmp);
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$display("Print irq = 0x%0x", tmp);
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$display("Print irq = 0x%0x", tmp);
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//Clearing all interrupts
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//Clearing all interrupts
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Line 324... |
Line 362... |
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end
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end
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`ifdef ETH_WISHBONE_B3
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integer single_cnt_tx, burst_cnt_tx, burst_cnt;
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integer single_cnt_rx, burst_cnt_rx;
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initial
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begin
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single_cnt_tx=0; burst_cnt_tx=0; burst_cnt=0;
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single_cnt_rx=0; burst_cnt_rx=0;
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end
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// Single and burst cycle watcher
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always @ (posedge wb_clk_o)
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begin
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if(eth_ma_wb_ack_i) begin
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if(eth_ma_wb_cyc_o & eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b000) begin
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if(burst_cnt!==0)
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$display("(%0t)(%m) ERROR !!! burst_cnt should be 0 because this is a single access", $time);
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else
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single_cnt_rx=single_cnt_rx+1;
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end
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else if(eth_ma_wb_cyc_o & !eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b000) begin
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if(burst_cnt!==0)
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$display("(%0t)(%m) ERROR !!! burst_cnt should be 0 because this is a single access", $time);
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else
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single_cnt_tx=single_cnt_tx+1;
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end
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else if(eth_ma_wb_cyc_o & eth_ma_wb_cti_o==3'b010) begin // burst in progress
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burst_cnt=burst_cnt+1;
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end
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else if(eth_ma_wb_cyc_o & eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b111 & burst_cnt==(`ETH_BURST_LENGTH-1)) begin
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burst_cnt_rx=burst_cnt_rx+1;
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burst_cnt=0;
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end
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else if(eth_ma_wb_cyc_o & !eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b111 & burst_cnt==(`ETH_BURST_LENGTH-1)) begin
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burst_cnt_tx=burst_cnt_tx+1;
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burst_cnt=0;
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end
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else
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$display("(%0t)(%m) ERROR !!! Unknown cycle type or sequence", $time);
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end
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end
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`endif // ETH_WISHBONE_B3
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task initialize_txbd;
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task initialize_txbd;
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input [6:0] txbd_num;
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input [6:0] txbd_num;
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integer i;
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integer i;
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