Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2001/08/06 14:44:29 mohor
|
|
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
|
|
// Include files fixed to contain no path.
|
|
// File names and module names changed ta have a eth_ prologue in the name.
|
|
// File eth_timescale.v is used to define timescale
|
|
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
|
|
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
|
|
// and Mdo_OE. The bidirectional signal must be created on the top level. This
|
|
// is done due to the ASIC tools.
|
|
//
|
// Revision 1.1 2001/07/30 21:23:42 mohor
|
// Revision 1.1 2001/07/30 21:23:42 mohor
|
// Directory structure changed. Files checked and joind together.
|
// Directory structure changed. Files checked and joind together.
|
//
|
//
|
// Revision 1.3 2001/06/19 18:16:40 mohor
|
// Revision 1.3 2001/06/19 18:16:40 mohor
|
// TxClk changed to MTxClk (as discribed in the documentation).
|
// TxClk changed to MTxClk (as discribed in the documentation).
|
Line 162... |
Line 172... |
wire RandomEqByteCnt;
|
wire RandomEqByteCnt;
|
wire PacketFinished_d;
|
wire PacketFinished_d;
|
|
|
|
|
|
|
assign ResetCollision = ~(StatePreamble | |StateData | StatePAD | StateFCS);
|
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
|
|
|
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
|
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
|
|
|
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & ~Pad & ~CrcEn);
|
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & ~Pad & ~CrcEn);
|
|
|
Line 341... |
Line 351... |
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
MTxEn <= #Tp 1'b0;
|
MTxEn <= #Tp 1'b0;
|
else
|
else
|
MTxEn <= #Tp StatePreamble | |StateData | StatePAD | StateFCS | StateJam;
|
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
end
|
end
|
|
|
|
|
// Transmit nibble
|
// Transmit nibble
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
Line 371... |
Line 381... |
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WillTransmit <= #Tp 1'b0;
|
WillTransmit <= #Tp 1'b0;
|
else
|
else
|
WillTransmit <= #Tp StartPreamble | StatePreamble | |StateData | StatePAD | StateFCS | StateJam;
|
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
end
|
end
|
|
|
|
|
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
|
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
|
|
|
Line 433... |
Line 443... |
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
|
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
|
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
|
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
|
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
|
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
|
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
|
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
|
|
|
assign Initialize_Crc = StateIdle | StatePreamble | |DlyCrcCnt;
|
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
|
|
|
|
|
// Connecting module Crc
|
// Connecting module Crc
|
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
|
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
|
.Crc(Crc), .CrcError(CrcError)
|
.Crc(Crc), .CrcError(CrcError)
|