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[/] [ethmac/] [tags/] [rel_9/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 106 and 119
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Rev 119 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.18 2002/05/03 10:15:50 mohor
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// Outputs registered. Reset changed for eth_wishbone module.
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//
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// Revision 1.17 2002/04/24 08:52:19 mohor
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// Revision 1.17 2002/04/24 08:52:19 mohor
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// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
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// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
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// bug fixed.
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// bug fixed.
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//
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//
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// Revision 1.16 2002/03/19 12:53:29 mohor
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// Revision 1.16 2002/03/19 12:53:29 mohor
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//
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//
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//
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//
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//
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//
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//`define EXTERNAL_DMA // Using DMA
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//`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
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//`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
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// Selection of the used memory
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// Selection of the used memory for Buffer descriptors
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//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
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//`define ETH_XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
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// specific elements.
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// specific elements.
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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