| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/09/24 15:02:56 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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//
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// Revision 1.2 2001/08/15 14:03:59 mohor
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// Revision 1.2 2001/08/15 14:03:59 mohor
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// Signal names changed on the top level for easier pad insertion (ASIC).
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// Signal names changed on the top level for easier pad insertion (ASIC).
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//
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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| Line 83... |
Line 89... |
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//RX
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//RX
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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// MIIM
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// MIIM
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mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o
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mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o,
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int_o
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);
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);
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| Line 135... |
Line 143... |
input md_pad_i; // MII data input (from I/O cell)
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input md_pad_i; // MII data input (from I/O cell)
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output mdc_pad_o; // MII Management data clock (to PHY)
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output mdc_pad_o; // MII Management data clock (to PHY)
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output md_pad_o; // MII data output (to I/O cell)
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output md_pad_o; // MII data output (to I/O cell)
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output md_padoen_o; // MII data output enable (to I/O cell)
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output md_padoen_o; // MII data output enable (to I/O cell)
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output int_o; // Interrupt output
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wire [7:0] r_ClkDiv;
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wire [7:0] r_ClkDiv;
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wire r_MiiNoPre;
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wire r_MiiNoPre;
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wire [15:0] r_CtrlData;
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wire [15:0] r_CtrlData;
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wire [4:0] r_FIAD;
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wire [4:0] r_FIAD;
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| Line 215... |
Line 224... |
wire TPauseRq; // Sinhronized Tx PAUSE request
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wire TPauseRq; // Sinhronized Tx PAUSE request
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wire [15:0] TxPauseTV; // Tx PAUSE timer value
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wire [15:0] TxPauseTV; // Tx PAUSE timer value
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wire r_TxFlow; // Tx flow control enable
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wire r_TxFlow; // Tx flow control enable
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire EthAddMatch;
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire WB_STB_I_eth;
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wire TxE_IRQ; // Interrupt Tx Error
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wire WB_CYC_I_eth;
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxF_IRQ; // Interrupt Rx Frame
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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wire DWord;
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wire DWord;
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wire RegAck;
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wire BDAck;
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wire BDAck;
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wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
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wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
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wire BDCs; // Buffer descriptor CS
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assign EthAddMatch = wb_adr_i[31:16] == `ETH_ETHERNET_SPACE;
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assign WB_STB_I_eth = wb_stb_i & EthAddMatch;
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assign WB_CYC_I_eth = wb_stb_i & EthAddMatch;
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assign wb_err_o = wb_stb_i & wb_cyc_i & EthAddMatch & ~DWord;
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assign DWord = &wb_sel_i;
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assign DWord = &wb_sel_i;
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & EthAddMatch & (wb_adr_i[15:12] == `ETH_REG_SPACE);
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[17] & ~wb_adr_i[16];
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assign RegAck = RegCs;
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[17] & wb_adr_i[16];
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assign wb_ack_o = RegAck | BDAck;
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assign wb_ack_o = RegCs | BDAck;
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assign wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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// Selecting the WISHBONE output data
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// Selecting the WISHBONE output data
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assign wb_dat_o[31:0] = (RegCs & ~wb_we_i)? RegDataOut : DMA_WB_DAT_O;
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assign wb_dat_o[31:0] = (RegCs & ~wb_we_i)? RegDataOut : DMA_WB_DAT_O;
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| Line 252... |
Line 258... |
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
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.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
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.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD),
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.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD),
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.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
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.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
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.r_IFG(r_IFG), .r_Pro(), .r_Iam(),
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.r_IFG(r_IFG), .r_Pro(), .r_Iam(),
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.r_Bro(), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
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.r_Bro(), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
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.r_RxEn(r_RxEn), .Busy_IRQ(), .RxF_IRQ(),
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.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ),
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.RxB_IRQ(), .TxE_IRQ(), .TxB_IRQ(),
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.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
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.Busy_MASK(), .RxF_MASK(), .RxB_MASK(),
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.r_IPGT(r_IPGT),
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.TxE_MASK(), .TxB_MASK(), .r_IPGT(r_IPGT),
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.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
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.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
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.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
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.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
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.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
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.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
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.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
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.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
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.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
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.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
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.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
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.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
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.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
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.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
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.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
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.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
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.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
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.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
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.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr)
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.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr), .int_o(int_o)
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);
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);
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wire [7:0] RxData;
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wire [7:0] RxData;
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| Line 477... |
Line 482... |
.WB_CLK_I(wb_clk_i), .WB_RST_I(wb_rst_i), .WB_DAT_I(wb_dat_i),
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.WB_CLK_I(wb_clk_i), .WB_RST_I(wb_rst_i), .WB_DAT_I(wb_dat_i),
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.WB_DAT_O(DMA_WB_DAT_O),
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.WB_DAT_O(DMA_WB_DAT_O),
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// WISHBONE slave
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// WISHBONE slave
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.WB_ADR_I(wb_adr_i), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
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.WB_ADR_I(wb_adr_i), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
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.WB_CYC_I(WB_CYC_I_eth), .WB_STB_I(WB_STB_I_eth), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
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.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
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.WB_RD_O(wb_rd_o),
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.WB_RD_O(wb_rd_o),
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//TX
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//TX
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.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
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.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
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| Line 495... |
Line 500... |
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDAddress(r_RxBDAddress),
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.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDAddress(r_RxBDAddress),
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.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr),
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.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr),
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//RX
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//RX
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm)
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ)
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);
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);
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// Connecting MacStatus module
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// Connecting MacStatus module
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