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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [README.txt] - Diff between revs 347 and 348
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RUNNING the simulation/Testbench in Icarus Verilog:
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RUNNING the simulation/Testbench in Icarus Verilog:
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Go to the scripts directory and write "make rtl-tests"
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Go to the scripts directory and write "make rtl-tests"
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All logs will be saved in the log directory
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All logs will be saved in the log directory
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VCD dumps are coming soon
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To activate VCD dumps, run with "make rtl-tests VCD=1". The VCD is saved
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in build/sim/ethmac.vcd
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RUNNING the simulation/Testbench in ModelSIM:
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RUNNING the simulation/Testbench in ModelSIM:
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Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
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Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
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Run the macro do.do (write "do do.do" in the command window).
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Run the macro do.do (write "do do.do" in the command window).
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