| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/07/19 13:57:53 mohor
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// Testing environment also includes traffic cop, memory interface and host
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// interface.
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//
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// Revision 1.2 2002/05/03 10:22:17 mohor
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// Revision 1.2 2002/05/03 10:22:17 mohor
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// TX_BUF_BASE changed.
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// TX_BUF_BASE changed.
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//
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//
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// Revision 1.1 2002/03/19 12:53:54 mohor
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// Revision 1.1 2002/03/19 12:53:54 mohor
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// Some defines that are used in testbench only were moved to tb_eth_defines.v
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// Some defines that are used in testbench only were moved to tb_eth_defines.v
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| Line 171... |
Line 175... |
`define ETH_CTRLMODER_TXFLOW 32'h00000004 /* Transmit Control Flow Enable */
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`define ETH_CTRLMODER_TXFLOW 32'h00000004 /* Transmit Control Flow Enable */
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/* MII Mode Register */
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/* MII Mode Register */
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`define ETH_MIIMODER_CLKDIV 32'h000000FF /* Clock Divider */
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`define ETH_MIIMODER_CLKDIV 32'h000000FF /* Clock Divider */
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`define ETH_MIIMODER_NOPRE 32'h00000100 /* No Preamble */
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`define ETH_MIIMODER_NOPRE 32'h00000100 /* No Preamble */
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`define ETH_MIIMODER_RST 32'h00000200 /* MIIM Reset */
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`define ETH_MIIMODER_RST 32'h00000400 /* MIIM Reset */
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/* MII Command Register */
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/* MII Command Register */
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`define ETH_MIICOMMAND_SCANSTAT 32'h00000001 /* Scan Status */
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`define ETH_MIICOMMAND_SCANSTAT 32'h00000001 /* Scan Status */
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`define ETH_MIICOMMAND_RSTAT 32'h00000002 /* Read Status */
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`define ETH_MIICOMMAND_RSTAT 32'h00000002 /* Read Status */
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`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
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`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
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