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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/07/25 17:19:06 mohor
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// Define ETH_MIIMODER_RST corrected to 0x00000400.
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//
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// Revision 1.3 2002/07/19 13:57:53 mohor
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// Revision 1.3 2002/07/19 13:57:53 mohor
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// Testing environment also includes traffic cop, memory interface and host
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// Testing environment also includes traffic cop, memory interface and host
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// interface.
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// interface.
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//
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//
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// Revision 1.2 2002/05/03 10:22:17 mohor
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// Revision 1.2 2002/05/03 10:22:17 mohor
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//
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//
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//
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//
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//
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//
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//`define VERBOSE // if log files of device modules are written
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//`define EXTERNAL_DMA // Using DMA
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//`define EXTERNAL_DMA // Using DMA
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`define MULTICAST_XFR 0
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`define MULTICAST_XFR 0
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`define UNICAST_XFR 1
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`define UNICAST_XFR 1
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`define BROADCAST_XFR 2
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`define BROADCAST_XFR 2
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`define ETH_IPGT `ETH_BASE + 32'h0C /* Back to Bak Inter Packet Gap Register */
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`define ETH_IPGT `ETH_BASE + 32'h0C /* Back to Bak Inter Packet Gap Register */
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`define ETH_IPGR1 `ETH_BASE + 32'h10 /* Non Back to Back Inter Packet Gap Register 1 */
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`define ETH_IPGR1 `ETH_BASE + 32'h10 /* Non Back to Back Inter Packet Gap Register 1 */
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`define ETH_IPGR2 `ETH_BASE + 32'h14 /* Non Back to Back Inter Packet Gap Register 2 */
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`define ETH_IPGR2 `ETH_BASE + 32'h14 /* Non Back to Back Inter Packet Gap Register 2 */
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`define ETH_PACKETLEN `ETH_BASE + 32'h18 /* Packet Length Register (min. and max.) */
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`define ETH_PACKETLEN `ETH_BASE + 32'h18 /* Packet Length Register (min. and max.) */
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`define ETH_COLLCONF `ETH_BASE + 32'h1C /* Collision and Retry Configuration Register */
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`define ETH_COLLCONF `ETH_BASE + 32'h1C /* Collision and Retry Configuration Register */
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`define ETH_RX_BD_NUM `ETH_BASE + 32'h20 /* Receive Buffer Descriptor Number Register */
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`define ETH_TX_BD_NUM `ETH_BASE + 32'h20 /* Transmit Buffer Descriptor Number Register */
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`define ETH_CTRLMODER `ETH_BASE + 32'h24 /* Control Module Mode Register */
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`define ETH_CTRLMODER `ETH_BASE + 32'h24 /* Control Module Mode Register */
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`define ETH_MIIMODER `ETH_BASE + 32'h28 /* MII Mode Register */
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`define ETH_MIIMODER `ETH_BASE + 32'h28 /* MII Mode Register */
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`define ETH_MIICOMMAND `ETH_BASE + 32'h2C /* MII Command Register */
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`define ETH_MIICOMMAND `ETH_BASE + 32'h2C /* MII Command Register */
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`define ETH_MIIADDRESS `ETH_BASE + 32'h30 /* MII Address Register */
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`define ETH_MIIADDRESS `ETH_BASE + 32'h30 /* MII Address Register */
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`define ETH_MIITX_DATA `ETH_BASE + 32'h34 /* MII Transmit Data Register */
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`define ETH_MIITX_DATA `ETH_BASE + 32'h34 /* MII Transmit Data Register */
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`define ETH_MIISTATUS `ETH_BASE + 32'h3C /* MII Status Register */
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`define ETH_MIISTATUS `ETH_BASE + 32'h3C /* MII Status Register */
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`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
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`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
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`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
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`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
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`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
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`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
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`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
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`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
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`define ETH_TX_CTRL `ETH_BASE + 32'h50 /* Tx Control Register */
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`define ETH_RX_CTRL `ETH_BASE + 32'h54 /* Rx Control Register */
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/* MODER Register */
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/* MODER Register */
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`define ETH_MODER_RXEN 32'h00000001 /* Receive Enable */
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`define ETH_MODER_RXEN 32'h00000001 /* Receive Enable */
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`define ETH_MODER_TXEN 32'h00000002 /* Transmit Enable */
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`define ETH_MODER_TXEN 32'h00000002 /* Transmit Enable */
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`define ETH_MODER_NOPRE 32'h00000004 /* No Preamble */
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`define ETH_MODER_NOPRE 32'h00000004 /* No Preamble */
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`define ETH_CTRLMODER_TXFLOW 32'h00000004 /* Transmit Control Flow Enable */
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`define ETH_CTRLMODER_TXFLOW 32'h00000004 /* Transmit Control Flow Enable */
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/* MII Mode Register */
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/* MII Mode Register */
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`define ETH_MIIMODER_CLKDIV 32'h000000FF /* Clock Divider */
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`define ETH_MIIMODER_CLKDIV 32'h000000FF /* Clock Divider */
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`define ETH_MIIMODER_NOPRE 32'h00000100 /* No Preamble */
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`define ETH_MIIMODER_NOPRE 32'h00000100 /* No Preamble */
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`define ETH_MIIMODER_RST 32'h00000400 /* MIIM Reset */
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`define ETH_MIIMODER_RST 32'h00000200 /* MIIM Reset */
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/* MII Command Register */
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/* MII Command Register */
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`define ETH_MIICOMMAND_SCANSTAT 32'h00000001 /* Scan Status */
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`define ETH_MIICOMMAND_SCANSTAT 32'h00000001 /* Scan Status */
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`define ETH_MIICOMMAND_RSTAT 32'h00000002 /* Read Status */
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`define ETH_MIICOMMAND_RSTAT 32'h00000002 /* Read Status */
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`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
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`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
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/* MII Address Register */
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/* MII Address Register */
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`define ETH_MIIADDRESS_FIAD 32'h0000001F /* PHY Address */
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`define ETH_MIIADDRESS_FIAD 32'h0000001F /* PHY Address */
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`define ETH_MIIADDRESS_RGAD 32'h00001F00 /* RGAD Address */
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`define ETH_MIIADDRESS_RGAD 32'h00001F00 /* RGAD Address */
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/* MII Status Register */
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/* MII Status Register */
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`define ETH_MIISTATUS_LINKFAIL 32'h00000001 /* Link Fail */
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`define ETH_MIISTATUS_LINKFAIL 0 /* Link Fail bit */
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`define ETH_MIISTATUS_BUSY 32'h00000002 /* MII Busy */
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`define ETH_MIISTATUS_BUSY 1 /* MII Busy bit */
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`define ETH_MIISTATUS_NVALID 32'h00000004 /* Data in MII Status Register is invalid */
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`define ETH_MIISTATUS_NVALID 2 /* Data in MII Status Register is invalid bit */
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No newline at end of file
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No newline at end of file
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