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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is available in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/09/13 11:57:20 mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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// Revision 1.3 2002/07/19 13:57:53 mohor
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// Revision 1.3 2002/07/19 13:57:53 mohor
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// Testing environment also includes traffic cop, memory interface and host
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// Testing environment also includes traffic cop, memory interface and host
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// interface.
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// interface.
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//
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//
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// Revision 1.2 2002/05/03 10:22:17 mohor
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// Revision 1.2 2002/05/03 10:22:17 mohor
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//`define VERBOSE // if log files of device modules are written
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//`define VERBOSE // if log files of device modules are written
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//`define EXTERNAL_DMA // Using DMA
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`define MULTICAST_XFR 0
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`define MULTICAST_XFR 0
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`define UNICAST_XFR 1
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`define UNICAST_XFR 1
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`define BROADCAST_XFR 2
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`define BROADCAST_XFR 2
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`define UNICAST_WRONG_XFR 3
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`define UNICAST_WRONG_XFR 3
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`define ETH_MIISTATUS `ETH_BASE + 32'h3C /* MII Status Register */
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`define ETH_MIISTATUS `ETH_BASE + 32'h3C /* MII Status Register */
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`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
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`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
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`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
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`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
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`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
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`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
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`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
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`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
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`define ETH_TX_CTRL `ETH_BASE + 32'h50 /* Tx Control Register */
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/* MODER Register */
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/* MODER Register */
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`define ETH_MODER_RXEN 32'h00000001 /* Receive Enable */
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`define ETH_MODER_RXEN 32'h00000001 /* Receive Enable */
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`define ETH_MODER_TXEN 32'h00000002 /* Transmit Enable */
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`define ETH_MODER_TXEN 32'h00000002 /* Transmit Enable */
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`define ETH_MODER_NOPRE 32'h00000004 /* No Preamble */
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`define ETH_MODER_NOPRE 32'h00000004 /* No Preamble */
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