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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Diff between revs 346 and 348
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Rev 346 |
Rev 348 |
Line 436... |
Line 436... |
$fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor error log =============");
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$fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor error log =============");
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$fdisplay(wb_m_mon_log_file_desc, " ");
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$fdisplay(wb_m_mon_log_file_desc, " ");
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$fdisplay(wb_m_mon_log_file_desc, " Only ERRONEOUS conditions are logged !");
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$fdisplay(wb_m_mon_log_file_desc, " Only ERRONEOUS conditions are logged !");
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$fdisplay(wb_m_mon_log_file_desc, " ");
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$fdisplay(wb_m_mon_log_file_desc, " ");
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`ifdef VCD
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$dumpfile("../build/sim/ethmac.vcd");
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$dumpvars(0);
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`endif
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// Reset pulse
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// Reset pulse
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wb_rst = 1'b1;
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wb_rst = 1'b1;
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#423 wb_rst = 1'b0;
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#423 wb_rst = 1'b0;
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// Clear memories
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// Clear memories
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