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[/] [ethmac/] [trunk/] [bench/] [verilog/] [wb_bus_mon.v] - Diff between revs 170 and 209

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`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/09/13 12:29:14 mohor`
	`// Headers changed.`
	`//`
`// Revision 1.1 2002/09/13 11:57:20 mohor`	`// Revision 1.1 2002/09/13 11:57:20 mohor`
`// New testbench. Thanks to Tadej M - "The Spammer".`	`// New testbench. Thanks to Tadej M - "The Spammer".`
`//`	`//`
`// Revision 1.1 2002/02/01 13:39:43 mihad`	`// Revision 1.1 2002/02/01 13:39:43 mihad`
`// Initial testbench import. Still under development`	`// Initial testbench import. Still under development`
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`// Revision 1.1 2001/08/06 18:12:58 mihad`	`// Revision 1.1 2001/08/06 18:12:58 mihad`
`// Pocasi delamo kompletno zadevo`	`// Pocasi delamo kompletno zadevo`
`//`	`//`
`//`	`//`

	`include "timescale.v"
`include "wb_model_defines.v"	`include "wb_model_defines.v"
`// WISHBONE bus monitor module - it connects to WISHBONE master signals and`	`// WISHBONE bus monitor module - it connects to WISHBONE master signals and`
`// monitors for any illegal combinations appearing on the bus.`	`// monitors for any illegal combinations appearing on the bus.`
`module WB_BUS_MON(`	`module WB_BUS_MON(`
`CLK_I,`	`CLK_I,`