URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_clockgen.v] - Diff between revs 352 and 353
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 352 |
Rev 353 |
| Line 85... |
Line 85... |
wire [7:0] CounterPreset;
|
wire [7:0] CounterPreset;
|
wire [7:0] TempDivider;
|
wire [7:0] TempDivider;
|
|
|
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|
|
|
|
// Counter counts half period
|
// Counter counts half period
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
