| Line 87... |
Line 87... |
s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,
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s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,
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s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
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s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
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s2_wb_dat_o
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s2_wb_dat_o
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);
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);
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|
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parameter Tp=1;
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parameter ETH_BASE = 32'hd0000000;
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parameter ETH_BASE = 32'hd0000000;
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parameter ETH_WIDTH = 32'h800;
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parameter ETH_WIDTH = 32'h800;
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parameter MEMORY_BASE = 32'h2000;
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parameter MEMORY_BASE = 32'h2000;
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parameter MEMORY_WIDTH = 32'h10000;
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parameter MEMORY_WIDTH = 32'h10000;
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| Line 164... |
Line 163... |
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if(wb_rst_i)
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if(wb_rst_i)
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begin
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begin
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m1_in_progress <=#Tp 0;
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m1_in_progress <= 0;
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m2_in_progress <=#Tp 0;
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m2_in_progress <= 0;
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s1_wb_adr_o <=#Tp 0;
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s1_wb_adr_o <= 0;
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s1_wb_sel_o <=#Tp 0;
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s1_wb_sel_o <= 0;
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s1_wb_we_o <=#Tp 0;
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s1_wb_we_o <= 0;
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s1_wb_dat_o <=#Tp 0;
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s1_wb_dat_o <= 0;
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s1_wb_cyc_o <=#Tp 0;
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s1_wb_cyc_o <= 0;
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s1_wb_stb_o <=#Tp 0;
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s1_wb_stb_o <= 0;
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s2_wb_adr_o <=#Tp 0;
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s2_wb_adr_o <= 0;
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s2_wb_sel_o <=#Tp 0;
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s2_wb_sel_o <= 0;
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s2_wb_we_o <=#Tp 0;
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s2_wb_we_o <= 0;
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s2_wb_dat_o <=#Tp 0;
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s2_wb_dat_o <= 0;
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s2_wb_cyc_o <=#Tp 0;
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s2_wb_cyc_o <= 0;
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s2_wb_stb_o <=#Tp 0;
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s2_wb_stb_o <= 0;
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end
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end
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else
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else
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begin
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begin
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case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
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case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
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5'b00_10_0, 5'b00_11_0 :
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5'b00_10_0, 5'b00_11_0 :
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begin
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begin
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m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
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m1_in_progress <= 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
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if(m1_addressed_s1)
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if(m1_addressed_s1)
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begin
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begin
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s1_wb_adr_o <=#Tp m1_wb_adr_i;
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s1_wb_adr_o <= m1_wb_adr_i;
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s1_wb_sel_o <=#Tp m1_wb_sel_i;
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s1_wb_sel_o <= m1_wb_sel_i;
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s1_wb_we_o <=#Tp m1_wb_we_i;
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s1_wb_we_o <= m1_wb_we_i;
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s1_wb_dat_o <=#Tp m1_wb_dat_i;
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s1_wb_dat_o <= m1_wb_dat_i;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_cyc_o <= 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
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s1_wb_stb_o <= 1'b1;
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end
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end
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else if(m1_addressed_s2)
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else if(m1_addressed_s2)
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begin
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begin
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s2_wb_adr_o <=#Tp m1_wb_adr_i;
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s2_wb_adr_o <= m1_wb_adr_i;
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s2_wb_sel_o <=#Tp m1_wb_sel_i;
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s2_wb_sel_o <= m1_wb_sel_i;
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s2_wb_we_o <=#Tp m1_wb_we_i;
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s2_wb_we_o <= m1_wb_we_i;
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s2_wb_dat_o <=#Tp m1_wb_dat_i;
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s2_wb_dat_o <= m1_wb_dat_i;
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s2_wb_cyc_o <=#Tp 1'b1;
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s2_wb_cyc_o <= 1'b1;
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s2_wb_stb_o <=#Tp 1'b1;
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s2_wb_stb_o <= 1'b1;
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end
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end
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else
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else
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$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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end
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end
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5'b00_01_0 :
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5'b00_01_0 :
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begin
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begin
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m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
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m2_in_progress <= 1'b1; // idle: m2 wants access: m2 -> m
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if(m2_addressed_s1)
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if(m2_addressed_s1)
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begin
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begin
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s1_wb_adr_o <=#Tp m2_wb_adr_i;
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s1_wb_adr_o <= m2_wb_adr_i;
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s1_wb_sel_o <=#Tp m2_wb_sel_i;
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s1_wb_sel_o <= m2_wb_sel_i;
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s1_wb_we_o <=#Tp m2_wb_we_i;
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s1_wb_we_o <= m2_wb_we_i;
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s1_wb_dat_o <=#Tp m2_wb_dat_i;
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s1_wb_dat_o <= m2_wb_dat_i;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_cyc_o <= 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
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s1_wb_stb_o <= 1'b1;
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end
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end
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else if(m2_addressed_s2)
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else if(m2_addressed_s2)
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begin
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begin
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s2_wb_adr_o <=#Tp m2_wb_adr_i;
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s2_wb_adr_o <= m2_wb_adr_i;
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s2_wb_sel_o <=#Tp m2_wb_sel_i;
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s2_wb_sel_o <= m2_wb_sel_i;
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s2_wb_we_o <=#Tp m2_wb_we_i;
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s2_wb_we_o <= m2_wb_we_i;
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s2_wb_dat_o <=#Tp m2_wb_dat_i;
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s2_wb_dat_o <= m2_wb_dat_i;
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s2_wb_cyc_o <=#Tp 1'b1;
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s2_wb_cyc_o <= 1'b1;
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s2_wb_stb_o <=#Tp 1'b1;
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s2_wb_stb_o <= 1'b1;
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end
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end
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else
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else
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$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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end
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end
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5'b10_10_1, 5'b10_11_1 :
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5'b10_10_1, 5'b10_11_1 :
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begin
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begin
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m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
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m1_in_progress <= 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
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if(m1_addressed_s1)
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if(m1_addressed_s1)
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begin
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begin
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s1_wb_cyc_o <=#Tp 1'b0;
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s1_wb_cyc_o <= 1'b0;
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s1_wb_stb_o <=#Tp 1'b0;
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s1_wb_stb_o <= 1'b0;
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end
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end
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else if(m1_addressed_s2)
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else if(m1_addressed_s2)
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begin
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begin
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s2_wb_cyc_o <=#Tp 1'b0;
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s2_wb_cyc_o <= 1'b0;
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s2_wb_stb_o <=#Tp 1'b0;
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s2_wb_stb_o <= 1'b0;
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end
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end
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end
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end
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5'b01_01_1, 5'b01_11_1 :
|
5'b01_01_1, 5'b01_11_1 :
|
begin
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begin
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m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
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m2_in_progress <= 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
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if(m2_addressed_s1)
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if(m2_addressed_s1)
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begin
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begin
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s1_wb_cyc_o <=#Tp 1'b0;
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s1_wb_cyc_o <= 1'b0;
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s1_wb_stb_o <=#Tp 1'b0;
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s1_wb_stb_o <= 1'b0;
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end
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end
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else if(m2_addressed_s2)
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else if(m2_addressed_s2)
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begin
|
begin
|
s2_wb_cyc_o <=#Tp 1'b0;
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s2_wb_cyc_o <= 1'b0;
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s2_wb_stb_o <=#Tp 1'b0;
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s2_wb_stb_o <= 1'b0;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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| Line 342... |
Line 341... |
// Activity monitor
|
// Activity monitor
|
integer cnt;
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integer cnt;
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
cnt <=#Tp 0;
|
cnt <= 0;
|
else
|
else
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if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
|
if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
|
cnt <=#Tp 0;
|
cnt <= 0;
|
else
|
else
|
if(s1_wb_cyc_o | s2_wb_cyc_o)
|
if(s1_wb_cyc_o | s2_wb_cyc_o)
|
cnt <=#Tp cnt+1;
|
cnt <= cnt+1;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if(cnt==1000) begin
|
if(cnt==1000) begin
|
