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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/03/25 13:33:04 mohor
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// When clear and read/write are active at the same time, cnt and pointers are
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// set to 1.
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//
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// Revision 1.1 2002/02/05 16:44:39 mohor
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// Revision 1.1 2002/02/05 16:44:39 mohor
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// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
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// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
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// MHz. Statuses, overrun, control frame transmission and reception still need
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// MHz. Statuses, overrun, control frame transmission and reception still need
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// to be fixed.
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// to be fixed.
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//
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//
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//
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//
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty);
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module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
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parameter DATA_WIDTH = 32;
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parameter DATA_WIDTH = 32;
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parameter DEPTH = 8;
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parameter DEPTH = 8;
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parameter CNT_WIDTH = 4;
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parameter CNT_WIDTH = 4;
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output [DATA_WIDTH-1:0] data_out;
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output [DATA_WIDTH-1:0] data_out;
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output almost_full;
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output almost_full;
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output full;
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output full;
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output almost_empty;
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output almost_empty;
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output empty;
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output empty;
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output [CNT_WIDTH-1:0] cnt;
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`ifdef ETH_FIFO_XILINX
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`else
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reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
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reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
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`endif
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reg [CNT_WIDTH-1:0] cnt;
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reg [CNT_WIDTH-1:0] cnt;
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reg [CNT_WIDTH-2:0] read_pointer;
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reg [CNT_WIDTH-2:0] read_pointer;
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reg [CNT_WIDTH-2:0] write_pointer;
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reg [CNT_WIDTH-2:0] write_pointer;
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assign empty = ~(|cnt);
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assign empty = ~(|cnt);
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assign almost_empty = cnt == 1;
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assign almost_empty = cnt == 1;
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assign full = cnt == DEPTH;
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assign full = cnt == DEPTH;
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assign almost_full = &cnt[CNT_WIDTH-2:0];
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assign almost_full = &cnt[CNT_WIDTH-2:0];
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`ifdef ETH_FIFO_XILINX
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xilinx_dist_ram_16x32 fifo
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( .data_out(data_out),
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.we(write & ~full),
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.data_in(data_in),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
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.wclk(clk)
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);
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`else
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if(write & clear)
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fifo[0] <=#Tp data_in;
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else
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if(write & ~full)
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if(write & ~full)
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fifo[write_pointer] <=#Tp data_in;
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fifo[write_pointer] <=#Tp data_in;
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end
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end
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assign data_out = fifo[read_pointer];
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assign data_out = clear ? fifo[0] : fifo[read_pointer];
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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