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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Diff between revs 40 and 94

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Rev 40	Rev 94
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/02/05 16:44:39 mohor`
	`// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200`
	`// MHz. Statuses, overrun, control frame transmission and reception still need`
	`// to be fixed.`
	`//`
`//`	`//`

`include "timescale.v"	`include "timescale.v"

`module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty);`	`module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty);`
Line 76...	Line 81...
`begin`	`begin`
`if(reset)`	`if(reset)`
`cnt <=#Tp 0;`	`cnt <=#Tp 0;`
`else`	`else`
`if(clear)`	`if(clear)`
`cnt <=#Tp 0;`	`cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};`
`else`	`else`
`if(read ^ write)`	`if(read ^ write)`
`if(read)`	`if(read)`
`cnt <=#Tp cnt - 1'b1;`	`cnt <=#Tp cnt - 1'b1;`
`else`	`else`
Line 91...	Line 96...
`begin`	`begin`
`if(reset)`	`if(reset)`
`read_pointer <=#Tp 0;`	`read_pointer <=#Tp 0;`
`else`	`else`
`if(clear)`	`if(clear)`
`read_pointer <=#Tp 0;`	`read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};`
`else`	`else`
`if(read & ~empty)`	`if(read & ~empty)`
`read_pointer <=#Tp read_pointer + 1'b1;`	`read_pointer <=#Tp read_pointer + 1'b1;`
`end`	`end`

Line 103...	Line 108...
`begin`	`begin`
`if(reset)`	`if(reset)`
`write_pointer <=#Tp 0;`	`write_pointer <=#Tp 0;`
`else`	`else`
`if(clear)`	`if(clear)`
`write_pointer <=#Tp 0;`	`write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};`
`else`	`else`
`if(write & ~full)`	`if(write & ~full)`
`write_pointer <=#Tp write_pointer + 1'b1;`	`write_pointer <=#Tp write_pointer + 1'b1;`
`end`	`end`

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Diff between revs 40 and 94