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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_miim.v] - Diff between revs 15 and 22
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Unconnected signals are now connected.
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// Unconnected signals are now connected.
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//
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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// Revision 1.3 2001/06/01 22:28:56 mohor
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// Revision 1.3 2001/06/01 22:28:56 mohor
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// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
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// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
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//
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//
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//
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//
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`include "eth_timescale.v"
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`include "timescale.v"
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module eth_miim
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module eth_miim
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(
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(
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Clk,
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Clk,
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