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// CVS Revision History

// CVS Revision History

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// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.4  2002/08/14 18:32:10  mohor

// Revision 1.4  2002/08/14 18:32:10  mohor

// - Busy signal was not set on time when scan status operation was performed

// - Busy signal was not set on time when scan status operation was performed

// and clock was divided with more than 2.

// and clock was divided with more than 2.

// - Nvalid remains valid two more clocks (was previously cleared too soon).

// - Nvalid remains valid two more clocks (was previously cleared too soon).

//

//

wire          MdcFrame;           // Frame window for limiting the Mdc

wire          MdcFrame;           // Frame window for limiting the Mdc

wire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.

wire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.

wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.

wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.

wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal

wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal

wire          LatchByte1_d2;

wire          LatchByte1_d2;

wire          LatchByte0_d2;

wire          LatchByte0_d2;

reg           LatchByte1_d;

reg           LatchByte1_d;

reg           LatchByte0_d;

reg           LatchByte0_d;