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[/ ] [ethmac/ ] [trunk/ ] [rtl/ ] [verilog/ ] [eth_outputcontrol.v ] - Diff between revs 37 and 109
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Rev 37
Rev 109
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
// simulation of the few cores in a one joined project.
//
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// Revision 1.1 2001/08/06 14:44:29 mohor
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// Generation of the Serial Enable signal (enables the serialization of the data)
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter> 31 | ( ( BitCounter == 0 ) & NoPre ) )
assign SerialEn = WriteOp & InProgress & ( BitCounter> 31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~ WriteOp & InProgress & ( ( BitCounter> 31 & BitCounter< 46 ) | ( ( BitCounter == 0 ) & NoPre ) ) ; // igor !!! ali je tu res <46. To je veljalo, ko sem imel se >31 in napako 32 preamble bitov
| ~ WriteOp & InProgress & ( ( BitCounter> 31 & BitCounter< 46 ) | ( ( BitCounter == 0 ) & NoPre ) ) ;
// Generation of the MdoEn signal
// Generation of the MdoEn signal
always @ ( posedge Clk or posedge Reset)
always @ ( posedge Clk or posedge Reset)
begin
begin
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