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`include "timescale.v"
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`include "timescale.v"
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module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
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module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
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parameter Tp = 1;
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input Clk; // Host Clock
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input Clk; // Host Clock
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input Reset; // General Reset
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input Reset; // General Reset
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input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
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input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
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input NoPre; // No Preamble (no 32-bit preamble)
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input NoPre; // No Preamble (no 32-bit preamble)
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input InProgress; // Operation in progress
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input InProgress; // Operation in progress
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// Generation of the MdoEn signal
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// Generation of the MdoEn signal
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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MdoEn_2d <= #Tp 1'b0;
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MdoEn_2d <= 1'b0;
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MdoEn_d <= #Tp 1'b0;
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MdoEn_d <= 1'b0;
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MdoEn <= #Tp 1'b0;
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MdoEn <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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if(MdcEn_n)
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if(MdcEn_n)
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begin
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begin
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MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
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MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
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MdoEn_d <= #Tp MdoEn_2d;
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MdoEn_d <= MdoEn_2d;
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MdoEn <= #Tp MdoEn_d;
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MdoEn <= MdoEn_d;
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end
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end
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end
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end
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end
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end
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// Generation of the Mdo signal.
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// Generation of the Mdo signal.
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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Mdo_2d <= #Tp 1'b0;
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Mdo_2d <= 1'b0;
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Mdo_d <= #Tp 1'b0;
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Mdo_d <= 1'b0;
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Mdo <= #Tp 1'b0;
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Mdo <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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if(MdcEn_n)
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if(MdcEn_n)
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begin
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begin
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Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
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Mdo_2d <= ~SerialEn & BitCounter<32;
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Mdo_d <= #Tp ShiftedBit | Mdo_2d;
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Mdo_d <= ShiftedBit | Mdo_2d;
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Mdo <= #Tp Mdo_d;
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Mdo <= Mdo_d;
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end
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end
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end
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end
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end
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end
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