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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_register.v] - Diff between revs 346 and 352
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Rev 346 |
Rev 352 |
Line 92... |
Line 92... |
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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DataOut<=#1 RESET_VALUE;
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DataOut<= RESET_VALUE;
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else
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else
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if(SyncReset)
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if(SyncReset)
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DataOut<=#1 RESET_VALUE;
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DataOut<= RESET_VALUE;
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else
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else
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if(Write) // write
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if(Write) // write
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DataOut<=#1 DataIn;
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DataOut<= DataIn;
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end
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end
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endmodule // Register
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endmodule // Register
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