| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2002/02/26 16:18:09 mohor
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// Reset values are passed to registers through parameters
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//
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// Revision 1.12 2002/02/17 13:23:42 mohor
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// Revision 1.12 2002/02/17 13:23:42 mohor
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// Define missmatch fixed.
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// Define missmatch fixed.
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//
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//
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// Revision 1.11 2002/02/16 14:03:44 mohor
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// Revision 1.11 2002/02/16 14:03:44 mohor
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// Registered trimmed. Unused registers removed.
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// Registered trimmed. Unused registers removed.
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| Line 448... |
Line 451... |
always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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irq_txb <= 1'b0;
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irq_txb <= 1'b0;
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else
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else
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if(TxB_IRQ & INT_MASKOut[0])
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if(TxB_IRQ)
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irq_txb <= #Tp 1'b1;
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irq_txb <= #Tp 1'b1;
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else
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else
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if(INT_SOURCE_Wr & DataIn[0])
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if(INT_SOURCE_Wr & DataIn[0])
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irq_txb <= #Tp 1'b0;
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irq_txb <= #Tp 1'b0;
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end
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end
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| Line 460... |
Line 463... |
always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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irq_txe <= 1'b0;
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irq_txe <= 1'b0;
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else
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else
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if(TxE_IRQ & INT_MASKOut[1])
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if(TxE_IRQ)
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irq_txe <= #Tp 1'b1;
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irq_txe <= #Tp 1'b1;
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else
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else
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if(INT_SOURCE_Wr & DataIn[1])
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if(INT_SOURCE_Wr & DataIn[1])
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irq_txe <= #Tp 1'b0;
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irq_txe <= #Tp 1'b0;
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end
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end
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| Line 472... |
Line 475... |
always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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irq_rxb <= 1'b0;
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irq_rxb <= 1'b0;
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else
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else
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if(RxB_IRQ & INT_MASKOut[2])
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if(RxB_IRQ)
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irq_rxb <= #Tp 1'b1;
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irq_rxb <= #Tp 1'b1;
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else
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else
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if(INT_SOURCE_Wr & DataIn[2])
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if(INT_SOURCE_Wr & DataIn[2])
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irq_rxb <= #Tp 1'b0;
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irq_rxb <= #Tp 1'b0;
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end
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end
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| Line 484... |
Line 487... |
always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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irq_rxe <= 1'b0;
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irq_rxe <= 1'b0;
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else
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else
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if(RxE_IRQ & INT_MASKOut[3])
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if(RxE_IRQ)
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irq_rxe <= #Tp 1'b1;
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irq_rxe <= #Tp 1'b1;
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else
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else
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if(INT_SOURCE_Wr & DataIn[3])
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if(INT_SOURCE_Wr & DataIn[3])
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irq_rxe <= #Tp 1'b0;
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irq_rxe <= #Tp 1'b0;
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end
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end
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| Line 496... |
Line 499... |
always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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irq_busy <= 1'b0;
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irq_busy <= 1'b0;
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else
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else
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if(Busy_IRQ & INT_MASKOut[4])
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if(Busy_IRQ)
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irq_busy <= #Tp 1'b1;
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irq_busy <= #Tp 1'b1;
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else
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else
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if(INT_SOURCE_Wr & DataIn[4])
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if(INT_SOURCE_Wr & DataIn[4])
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irq_busy <= #Tp 1'b0;
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irq_busy <= #Tp 1'b0;
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end
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end
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| Line 508... |
Line 511... |
always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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irq_txc <= 1'b0;
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irq_txc <= 1'b0;
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else
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else
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if(TxC_IRQ & INT_MASKOut[5])
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if(TxC_IRQ)
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irq_txc <= #Tp 1'b1;
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irq_txc <= #Tp 1'b1;
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else
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else
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if(INT_SOURCE_Wr & DataIn[5])
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if(INT_SOURCE_Wr & DataIn[5])
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irq_txc <= #Tp 1'b0;
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irq_txc <= #Tp 1'b0;
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end
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end
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| Line 520... |
Line 523... |
always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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irq_rxc <= 1'b0;
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irq_rxc <= 1'b0;
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else
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else
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if(RxC_IRQ & INT_MASKOut[6])
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if(RxC_IRQ)
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irq_rxc <= #Tp 1'b1;
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irq_rxc <= #Tp 1'b1;
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else
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else
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if(INT_SOURCE_Wr & DataIn[6])
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if(INT_SOURCE_Wr & DataIn[6])
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irq_rxc <= #Tp 1'b0;
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irq_rxc <= #Tp 1'b0;
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end
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end
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// Generating interrupt signal
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// Generating interrupt signal
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assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxe | irq_busy | irq_txc | irq_rxc;
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assign int_o = irq_txb & INT_MASKOut[0] |
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irq_txe & INT_MASKOut[1] |
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irq_rxb & INT_MASKOut[2] |
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irq_rxe & INT_MASKOut[3] |
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irq_busy & INT_MASKOut[4] |
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irq_txc & INT_MASKOut[5] |
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irq_rxc & INT_MASKOut[6] ;
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// For reading interrupt status
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// For reading interrupt status
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assign INT_SOURCEOut = {26'h0, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
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assign INT_SOURCEOut = {26'h0, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
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