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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 139 and 140
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Rev 140 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2002/08/16 22:14:22 mohor
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// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
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// changed from bit position 10 to 9.
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//
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// Revision 1.15 2002/08/14 18:26:37 mohor
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// Revision 1.15 2002/08/14 18:26:37 mohor
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// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
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// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
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//
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//
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// Revision 1.14 2002/04/22 14:03:44 mohor
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// Revision 1.14 2002/04/22 14:03:44 mohor
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// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
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// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
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Line 464... |
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// MIITX_DATA Register
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// MIITX_DATA Register
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eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
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eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
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(
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(
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.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
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.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
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.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0])
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.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
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.Write (MIITX_DATA_Wr),
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.Write (MIITX_DATA_Wr),
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.Clk (Clk),
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.Clk (Clk),
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.Reset (Reset),
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.Reset (Reset),
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.SyncReset (0)
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.SyncReset (0)
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);
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);
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