| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.22 2002/11/14 18:37:20 mohor
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// r_Rst signal does not reset any module any more and is removed from the design.
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//
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// Revision 1.21 2002/09/10 10:35:23 mohor
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// Revision 1.21 2002/09/10 10:35:23 mohor
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// Ethernet debug registers removed.
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// Ethernet debug registers removed.
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//
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//
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// Revision 1.20 2002/09/04 18:40:25 mohor
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// Revision 1.20 2002/09/04 18:40:25 mohor
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// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
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// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
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| Line 143... |
Line 146... |
r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
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r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
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StartTxDone, TxClk, RxClk, ReceivedPauseFrm
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StartTxDone, TxClk, RxClk, ReceivedPauseFrm
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| Line 211... |
Line 214... |
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output r_TxFlow;
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output r_TxFlow;
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output r_RxFlow;
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output r_RxFlow;
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output r_PassAll;
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output r_PassAll;
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output r_MiiMRst;
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output r_MiiNoPre;
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output r_MiiNoPre;
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output [7:0] r_ClkDiv;
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output [7:0] r_ClkDiv;
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output r_WCtrlData;
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output r_WCtrlData;
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output r_RStat;
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output r_RStat;
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| Line 680... |
Line 682... |
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assign r_TxFlow = CTRLMODEROut[2];
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assign r_TxFlow = CTRLMODEROut[2];
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assign r_RxFlow = CTRLMODEROut[1];
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assign r_RxFlow = CTRLMODEROut[1];
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assign r_PassAll = CTRLMODEROut[0];
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assign r_PassAll = CTRLMODEROut[0];
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assign r_MiiMRst = MIIMODEROut[9];
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assign r_MiiNoPre = MIIMODEROut[8];
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assign r_MiiNoPre = MIIMODEROut[8];
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assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
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assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
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assign r_WCtrlData = MIICOMMANDOut[2];
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assign r_WCtrlData = MIICOMMANDOut[2];
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assign r_RStat = MIICOMMANDOut[1];
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assign r_RStat = MIICOMMANDOut[1];
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